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hd66740 1 hd66740 (112 x 80-dot graphics lcd controller/driver) rev 1. 0 a u gu st , 2001 description the hd66740, 112-by-80 dot-matrix graphics lcd controller and driver lsi, displays graphics such as text, kanji and pictograms. it can be configured to drive a dot-matrix liquid crystal under the control of the m i c r op r o c e s s o r c onn e c t e d v i a t h e c l o c k - s yn c h r on i z e d s e r i a l o r 4 / 8 - b i t bu s . t h e h d 66740 h a s a s m oo t h vertical scroll display and a double-height display for the remaining bit map areas. it fixed-displays a part of the graphics icons so that the user can easily see a variety of information. t h e h d 66740 h a s v a r i ou s f un c t i on s t o r e du c e t h e po w e r c on s u m p t i on o f a n l c d s y s t e m s u c h a s l o w - voltage operation of 1.8 v min., a booster to generate maximum five-times lcd drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the lcd drive bleeder- resistors. combining these hardware functions with software functions such as standby and sleep modes allows fine power control. the hd66740 is suitable for any portable battery-driven product requiring long-term driving capabilities such as cellular phones, pagers, or electronic wallets. features control and drive of a graphics lcd 112 x 80-dot display fixed display of graphics icons (pictograms) low-power operation support: ? vcc = 1.8 to 3.6 v (low voltage) ? v lcd = 4.5 to 15.0 v (liquid crystal drive voltage) ? triple, quadruple, or five-times booster for liquid crystal drive voltage ? 64-step contrast adjuster and voltage followers to decrease direct current flow in the lcd drive bleeder-resistors ? power-save functions such as the standby mode and sleep mode supported ? programmable drive duty ratios and bias values displayed on lcd high-speed clock-synchronized serial interface (serial transfer rate: 5 mhz max.) i2c bus interface high-speed 4-/8-bit bus interface capability 112-segment 80-common liquid crystal display driver 1,120-byte (112 80 dots) character generator ram
hd66740 2 vertical smooth scroll partial smooth scroll control (fixed display of graphics icons) vertical double-height display by each display line black-and-white reversed display wide range of instruction functions: ? display on/off control, black-and-white reversed no wait time for instruction execution and ram access internal oscillation and hardware reset n-raster-row ac liquid-crystal drive (c-pattern waveform drive) shift change of segment and common driver tape carrier package (tcp) table 1 progammable display sizes and duty ratios graphics display duty ratio optimum drive bias bit map 12 x 13-dot font width 14 x 15-dot font width 16 x 16-dot font width 1/32 1/7 112 x 32 dots 2 lines x 9 characters 2 lines x 8 characters 2 lines x 7 characters 1/40 1/7 112 x 40 dots 3 lines x 9 characters 2.5 lines x 8 characters 2.5 lines x 7 characters 1/48 1/8 112 x 48 dots 3 lines x 9 characters 3 lines x 8 characters 3 line x 7 characters 1/56 1/8 112 x 56 dots 4 lines x 9 characters 3.5 lines x 8 characters 3.5 lines x 7 characters 1/64 1/9 112 x 64 dots 5 lines x 9 characters 4 lines x 8 characters 4 lines x 7 characters 1/72 1/9.5 112 x 72 dots 6 lines x 9 characters 4.5 lines x 8 characters 4.5 lines x 7 characters 1/80 1/10 112 x 80 dots 6 lines x 9 characters 5 lines x 8 characters 5 lines x 7 characters
hd66740 3 total current consumption characteristics (vcc = 3 v, typ conditions, lcd drive power current included) total power consumption normal display operation character display dot size duty ratio r-c oscillation frequency frame frequency internal logic lcd power total* sleep mode standby mode 112 x 32 dots 1/32 75 khz 73 hz (27 a) (16 a) triple (75 a) (15 a) 0.1 a 112 x 40 dots 1/40 75 khz 73 hz (27 a) (16 a) triple (75 a) (15 a) 112 x 48 dots 1/48 75 khz 74 hz (27 a) (16 a) triple (75 a) (15 a) 112 x 56 dots 1/56 75 khz 74 hz (27 a) (16 a) triple (75 a) (15 a) 112 x 64 dots 1/64 75 khz 73 hz (27 a) (18 a) quadruple (99 a) (15 a) 112 x 72 dots 1/72 80 khz 70 hz (32 a) (18 a) quadruple (104 a) (15 a) 112 x 80 dots 1/80 90 khz 70 hz (35 a) (20 a) five-times (135 a) (15 a) note : when a triple, quadruple, or five-times booster is used: the total power consumption = internal logic current + lcd power current x 3 (triple booster), the total power consumption = internal logic current + lcd power current x 4 (quadruple booster), and the total power consumption = internal logic current + lcd power current x 5 (five-times booster) type name types external dimensions bus interface operation voltages hd66740tb0 bending tcp 4/8-bits parallel and clock synchronized serial hd66740wtb0 bending tcp 4/8-bits parallel and i2c bus interface HCD66740bp au-bumped chip 4/8-bits parallel and clock synchronized serial HCD66740wbp au-bumped chip 4/8-bits parallel and i2c bus interface 1.8 v to 3.6 v
hd66740 4 lcd specification comparison (under development) items hd66725 hd66728 hd66740 character display sizes 16 characters x 3 lines 16 characters x 10 lines graphic display sizes 96 x 26 dots 112 x 80 dots 112 x 80 dots multiplexing icons 192 annunciator 1/2 duty: 192 key scan control 8 x 4 8 x 4 led control ports general output ports 3 3 operating power voltages 1.8 v to 5.5 v 1.8 v to 5.5 v 1.8 v to 3.6 v liquid crystal drive voltages 3 v to 6 v 4.5 v to 15 v 4.5 v to 15 v i2c bus i2c bus interface (hd66740w) serial bus clock-synchronized serial clock-synchronized serial clock-synchronized serial parallel bus 4 bits, 8 bits 4 bits, 8 bits 4 bits, 8 bits expansion driver control impossible impossible impossible liquid crystal drive duty ratios 1/2, 10, 18, 26 1/8, 16, 24, 32, 40, 48, 56, 6 4 72, 80 1/8, 16, 24, 32, 40, 48, 56, 6 4 72, 80 liquid crystal drive biases 1/4 to 1/6.5 1/4 to 1/10 1/4 to 1/10 liquid crystal drive waveforms b b, c b, c liquid crystal voltage booster single, double, or triple triple, quadruple, or five- times triple, quadruple, or five- times bleeder-resistor for liquid crystal drive incorporated (external) incorporated (external) incorporated (external) liquid crystal drive operational amplifier incorporated incorporated incorporated liquid crystal contrast adjuster incorporated incorporated incorporated horizontal smooth scroll 3-dot unit vertical smooth scroll line unit line unit line unit double-height display yes yes yes ddram 80 x 8 160 x 8 cgrom 20,736 20,736 cgram 384 x 8 1,120 x 8 1,120 x 8 segram 96 x 8 no. of cgrom fonts 240 + 192 240 + 192 no. of cgram fonts 64 64 font sizes 6 x 8 6 x 8 bit map areas 96 x 26 112 x 80 112 x 80 r-c oscillation resistor/ oscillation frequency external resistor, incorporated (32 khz) external resistor (70C90 khz) external resistor (70C90 khz) reset function external external external low power control partial display off oscillation off liquid crystal power off key wake-up interrupt partial display off oscillation off liquid crystal power off key wake-up interrupt partial display off oscillation off liquid crystal power off seg/com direction switching seg, com seg, com seg, com qfp package tqfp package tcp package tcp-170 tcp-243 tcp-233 bare chip bumped chip yes yes yes no. of pins 170 243 243 chip sizes 10.97 x 2.51 13.67 x 2.78 9.40 x 2.18 pad intervals 80 m 70 m 50 m
hd66740 5 hd66740 block diagram system interface - clock synchro- nized serial - i2c bus - 4-bit bus - 8-bit bus data register (dr) instruction register (ir) address counter (ac) timing generator character generator ram (cgram) 1,120 bytes parallel/serial converter 112-bit latch circuit 112-bit segment shift register 80-bit bidirectional common shift register common driver segment driver lcd drive voltage selector cpg instruction decoder rs rw/rd*/sda e/wr*/scl vcc v lcd com1/80e com80/1 seg1/112 e seg112/1 osc1 osc2 8 8 8 10 8 vci triple to five-times booster c1+ im2-1 reset* c1- +- +- +- +- vlout +- gnd vr rrr 0 r test v1out v2out v3out v4out v5out opoff im0/id c2+ c2- cs* c3+ c3- contrast adjuster drive bias controller c4+ c4- vtest1e vtest3 db0-db7
hd66740 6 hd66740 pad arrangement rev 0.5 - chip size : 9.40mm x 2.18mm - chip thickness : 550um (typ.) - pad coordinates : pad center - coodinate origin : chip center - au bump size (pin number is shown in the b lacket) ( 1)80um x 80um dummy1(1) to dummy2(78), dummy3(104), dummy20(263) ( 2)45um x 80um com34(105) to com80(119) dummy4(120) dummy5(121) to dummy10(126) dummy13(241) to dummy18(246) dummy19(247) com72(248) to com58(262) ( 3)80um x 45um com57(264) to com1(288) com9(79) to com33(103) ( 4)35um x 80um dummy11(127) seg1(128) to seg112(239) dummy12(240) - au bump pitch: refer pad coodinate - au bump height : 15um(typ.) - no cross recognition mark (top view) hd66740 osc2 osc1 v c i y x c2 - c2 + c2+ vci v c i v cc e/wr*/scl vtest 3 vtest 2 vtest1 gnddum2 c1- c1 - vlout vlout v lcd v lcd c1 + v cc vcc rw/rd*/sda gnd gnd gnd rs cs* reset* db0 db1 db2 db3 db4 db5 db6 db7 gnddum im2 im1 im0/id vccdum opof f test c3 - c3 - c3 + c3 + v1out v2out v3out v4out v5out com1/80 com2/79 com3/78 com4/77 com6/75 com7/74 com8/73 com41/40 com42/39 com43/38 com44/37 com5/76 com45/36 com46/35 com47/34 com48/33 com49/32 com50/31 com51/30 com52/29 com53/28 com54/27 com55/26 com56/25 com14/67 com15/66 com16/65 com17/64 com18/63 com19/62 com21/60 com22/59 com23/58 com24/57 com25/56 com26/55 com27/54 com28/53 com20/61 com29/52 com30/51 com13/68 com12/69 com11/70 com10/71 com31/50 com32/49 seg9/104 seg8/105 seg7/106 seg6/107 seg5/108 seg4/109 seg101/12 seg102/11 seg103/10 seg104/9 seg105/8 seg106/7 seg107/6 seg108/5 seg109/4 seg112/1 seg111/2 seg1/112 seg2/111 seg3/110 seg110/3 com57/24 com33/48 seg10/103 seg11/102 seg100/13 seg99/14 seg12/101 seg13/100 seg14/99 c4 - c4 - c4 + c4 + com72/9 com71/10 com70/11 com69/12 com68/13 com67/14 com66/15 com58/23 com59/22 com60/21 com61/20 com62/19 com63/18 com64/17 com65/16 com80/1 com79/2 com78/3 com77/4 com76/5 com75/6 com74/7 com34/47 com35/46 com36/45 com37/44 com38/43 com39/42 com40/41 com73/8 dummy1 seg25/88 seg26/87 seg27/86 seg28/85 seg29/84 seg30/83 seg31/82 seg32/81 seg33/80 seg34/79 seg35/78 seg36/77 seg37/76 seg38/75 seg39/74 seg40/73 seg41/72 seg42/71 seg43/70 seg44/69 seg45/68 seg46/67 seg47/66 seg48/65 seg49/64 seg50/63 seg51/62 seg52/61 seg53/60 seg54/59 seg55/58 seg56/57 seg57/56 seg58/55 seg59/54 seg60/53 seg61/52 seg62/51 seg63/50 seg64/49 seg65/48 seg66/47 seg67/46 seg68/45 seg69/44 seg70/43 seg71/42 seg72/41 seg73/40 seg74/39 seg75/38 seg76/37 seg77/36 seg78/35 seg79/34 seg80/33 seg81/32 seg82/31 seg83/30 seg84/29 seg85/28 seg86/27 seg87/26 seg88/25 seg89/24 seg90/23 seg91/22 seg92/21 seg93/20 seg94/19 seg95/18 seg96/17 seg97/16 seg98/15 seg24/89 seg23/90 seg22/91 seg21/92 seg20/93 seg19/94 seg18/95 seg17/96 seg16/97 seg15/98 com9/72 c1+ c2 - vlout v lcd d ummy 2 d ummy 3 d ummy 4 d ummy 5 d ummy 6 d ummy 7 d ummy 11 dummy20 vcc gnd c3 + c4 - c4+ c2 - c2 + c1 - vlout v lcd c1 + c3 - d ummy 8 d ummy 9 d ummy 12 dumm y 13 dummy14 d ummy 15 d ummy 19 d ummy 16 d ummy 17 v c i dummy10 d ummy 18 gnd hd66740 type code no.1 no.2 no.288 n o .78 n o .77 n o .79 n o .103 n o .104 n o .105 no.262 no.263 no.264
hd66740 7 hd66740 pad coordinate 2000.06.13 (unit : um) no. pad name x y no. pad name x y no. pad name x y no. pad name x y 1 dummy1 -4538 -930 73 v5out 3834 -930 145 seg18/95 1930 928 217 seg90/23 -1679 928 2 gnddum -4336 -930 74 vtest1 3936 -930 146 seg19/94 1880 928 218 seg91/22 -1729 928 3 im2 -4190 -930 75 vtest2 4038 -930 147 seg20/93 1829 928 219 seg92/21 -1779 928 4 im1 -4045 -930 76 vtest3 4140 -930 148 seg21/92 1779 928 220 seg93/20 -1829 928 5 i m0/id -3915 -930 77 gnddum2 4336 -930 149 seg22/91 1729 928 221 seg94/19 -1880 928 6 vccdum -3813 -930 78 dummy2 4538 -930 150 seg23/90 1679 928 222 seg95/18 -1930 928 7 opoff -3711 -930 79 com9/72 4538 -721 151 seg24/89 1629 928 223 seg96/17 -1980 928 8 test -3609 -930 80 com 10/71 4538 -661 152 seg25/88 1579 928 224 seg97/16 -2030 928 9 db7 -3466 -930 81 com 11/70 4538 -601 153 seg26/87 1529 928 225 seg98/15 -2080 928 10 db6 -3321 -930 82 com 12/69 4538 -541 154 seg27/86 1479 928 226 seg99/14 -2130 928 11 db5 -3177 -930 83 com 13/68 4538 -481 155 seg28/85 1428 928 227 seg100/13 -2180 928 12 db4 -3032 -930 84 com 14/67 4538 -421 156 seg29/84 1378 928 228 seg101/12 -2230 928 13 db3 -2887 -930 85 com 15/66 4538 -361 157 seg30/83 1328 928 229 seg102/11 -2281 928 14 db2 -2742 -930 86 com 16/65 4538 -301 158 seg31/82 1278 928 230 seg103/10 -2331 928 15 db1 -2597 -930 87 com 17/64 4538 -240 159 seg32/81 1228 928 231 seg104/9 -2381 928 16 db0 -2453 -930 88 com 18/63 4538 -180 160 seg33/80 1178 928 232 seg105/8 -2431 928 17 reset* -2308 -930 89 com 19/62 4538 -120 161 seg34/79 1128 928 233 seg106/7 -2481 928 18 cs* -2163 -930 90 com 20/61 4538 -60 162 seg35/78 1078 928 234 seg107/6 -2531 928 19 rs -2018 -930 91 com 21/60 4538 0 163 seg36/77 1028 928 235 seg108/5 -2581 928 20 e/wr*/scl -1873 -930 92 com 22/59 4538 60 164 seg37/76 977 928 236 seg109/4 -2631 928 21 rw/rd*/sda -1729 -930 93 com 23/58 4538 120 165 seg38/75 927 928 237 seg110/3 -2682 928 22 gnd -1627 -930 94 com 24/57 4538 180 166 seg39/74 877 928 238 seg111/2 -2732 928 23 gnd -1525 -930 95 com 25/56 4538 240 167 seg40/73 827 928 239 seg112/1 -2782 928 24 gnd -1423 -930 96 com 26/55 4538 301 168 seg41/72 777 928 240 dummy12 -2836 928 25 gnd -1321 -930 97 com 27/54 4538 361 169 seg42/71 727 928 241 dummy13 -2981 928 26 gnd -1219 -930 98 com 28/53 4538 421 170 seg43/70 677 928 242 dummy14 -3041 928 27 osc2 -1117 -930 99 com 29/52 4538 481 171 seg44/69 627 928 243 dummy15 -3101 928 28 osc1 -972 -930 100 com 30/51 4538 541 172 seg45/68 576 928 244 dummy16 -3161 928 29 vcc -791 -930 101 com 31/50 4538 601 173 seg46/67 526 928 245 dummy17 -3221 928 30 vcc -689 -930 102 com 32/49 4538 661 174 seg47/66 476 928 246 dummy18 -3281 928 31 vcc -587 -930 103 com 33/48 4538 721 175 seg48/65 426 928 247 dummy19 -3431 928 32 vcc -485 -930 104 dummy3 4538 928 176 seg49/64 376 928 248 com72/9 -3495 928 33 vci -332 -930 105 com 34/47 4336 928 177 seg50/63 326 928 249 com 71/10 -3555 928 34 vci -230 -930 106 com 35/46 4276 928 178 seg51/62 276 928 250 com 70/11 -3615 928 35 vci -128 -930 107 com 36/45 4216 928 179 seg52/61 226 928 251 com 69/12 -3675 928 36 vci -26 -930 108 com 37/44 4156 928 180 seg53/60 175 928 252 com 68/13 -3735 928 37 c4+ 76 -930 109 com 38/43 4096 928 181 seg54/59 125 928 253 com 67/14 -3795 928 38 c4+ 178 -930 110 com 39/42 4036 928 182 seg55/58 75 928 254 com 66/15 -3856 928 39 c4+ 280 -930 111 com 40/41 3976 928 183 seg56/57 25 928 255 com 65/16 -3916 928 40 c4- 381 -930 112 com73/8 3916 928 184 seg57/56 -25 928 256 com 64/17 -3976 928 41 c4- 483 -930 113 com74/7 3856 928 185 seg58/55 -75 928 257 com 63/18 -4036 928 42 c4- 585 -930 114 com75/6 3795 928 186 seg59/54 -125 928 258 com 62/19 -4096 928 43 c3+ 687 -930 115 com76/5 3735 928 187 seg60/53 -175 928 259 com 61/20 -4156 928 44 c3+ 789 -930 116 com77/4 3675 928 188 seg61/52 -226 928 260 com 60/21 -4216 928 45 c3+ 891 -930 117 com78/3 3615 928 189 seg62/51 -276 928 261 com 59/22 -4276 928 46 c3- 993 -930 118 com79/2 3555 928 190 seg63/50 -326 928 262 com 58/23 -4336 928 47 c3- 1095 -930 119 com80/1 3495 928 191 seg64/49 -376 928 263 dummy20 -4538 928 48 c3- 1197 -930 120 dummy4 3431 928 192 seg65/48 -426 928 264 com 57/24 -4538 721 49 c2+ 1299 -930 121 dummy5 3281 928 193 seg66/47 -476 928 265 com 56/25 -4538 661 50 c2+ 1401 -930 122 dummy6 3221 928 194 seg67/46 -526 928 266 com 55/26 -4538 601 51 c2+ 1503 -930 123 dummy7 3161 928 195 seg68/45 -576 928 267 com 54/27 -4538 541 52 c2- 1605 -930 124 dummy8 3101 928 196 seg69/44 -627 928 268 com 53/28 -4538 481 53 c2- 1707 -930 125 dummy9 3041 928 197 seg70/43 -677 928 269 com 52/29 -4538 421 54 c2- 1809 -930 126 dummy10 2981 928 198 seg71/42 -727 928 270 com 51/30 -4538 361 55 c1+ 1911 -930 127 dummy11 2836 928 199 seg72/41 -777 928 271 com 50/31 -4538 301 56 c1+ 2013 -930 128 seg1/112 2782 928 200 seg73/40 -827 928 272 com 49/32 -4538 240 57 c1+ 2115 -930 129 seg2/111 2732 928 201 seg74/39 -877 928 273 com 48/33 -4538 180 58 c1- 2217 -930 130 seg3/110 2682 928 202 seg75/38 -927 928 274 com 47/34 -4538 120 59 c1- 2319 -930 131 seg4/109 2631 928 203 seg76/37 -977 928 275 com 46/35 -4538 60 60 c1- 2421 -930 132 seg5/108 2581 928 204 seg77/36 -1028 928 276 com 45/36 -4538 0 61 vlout 2523 -930 133 seg6/107 2531 928 205 seg78/35 -1078 928 277 com 44/37 -4538 -60 62 vlout 2625 -930 134 seg7/106 2481 928 206 seg79/34 -1128 928 278 com 43/38 -4538 -120 63 vlout 2727 -930 135 seg8/105 2431 928 207 seg80/33 -1178 928 279 com 42/39 -4538 -180 64 vlout 2829 -930 136 seg9/104 2381 928 208 seg81/32 -1228 928 280 com 41/40 -4538 -240 65 vlcd 2930 -930 137 seg10/103 2331 928 209 seg82/31 -1278 928 281 com8/73 -4538 -301 66 vlcd 3032 -930 138 seg11/102 2281 928 210 seg83/30 -1328 928 282 com7/74 -4538 -361 67 vlcd 3134 -930 139 seg12/101 2230 928 211 seg84/29 -1378 928 283 com6/75 -4538 -421 68 vlcd 3236 -930 140 seg13/100 2180 928 212 seg85/28 -1428 928 284 com5/76 -4538 -481 69 v1out 3426 -930 141 seg14/99 2130 928 213 seg86/27 -1479 928 285 com4/77 -4538 -541 70 v2out 3528 -930 142 seg15/98 2080 928 214 seg87/26 -1529 928 286 com3/78 -4538 -601 71 v3out 3630 -930 143 seg16/97 2030 928 215 seg88/25 -1579 928 287 com2/79 -4538 -661 72 v4out 3732 -930 144 seg17/96 1980 928 216 seg89/24 -1629 928 288 com1/80 -4538 -721
hd66740 8 tcp dimensions (hd66740tb0) com1/80 com8/73 seg112/1 seg1/112 com9/72 0.16-mm pitch hitachi hitachi hd66740 hd66740 com41/40 com72/9 im2 im1 im0/id opoff test nc nc nc nc nc db7 db6 db5 db4 db3 db2 db1 db0 reset* cs* rs e/wr*/scl rw/rd*/sda gnd osc2 osc1 vcc vci c2+ c2- c1+ c1- vlout vlcd v1out v2out v3out v4out v5out nc nc nc vtest1 vtset2 vtest3 0.65-mm pitch dummy dummy c3+ c3- com80/1 com73/8 com40/41 bending slit 4.0 mm 0.17p x (41 ?1) = 6.80 mm 0.17p x (41 ?1) = 6.80 mm 0.50 mm 0.50 mm 32.36 mm seg111/2 seg110/3 seg109/4 seg2/111 seg3/110 seg4/109 c4+ c4- i/o, power supply 0.65p x (49 ?1) = 31.20 mm lcd drive 0.16p x (112 ?1) = 17.76 mm
hd66740 9 pin functions table 2 pin functional description signals number of pins i/o connected to functions im2, im1 2 i gnd or v cc selects the mpu interface mode: im2 "gnd" "gnd" "vcc" "vcc" im1 "gnd" "vcc" "gnd" "vcc" mpu interface mode clock synchronized serial interface 68-system parallel interface i2c bus interface 80-system parallel interface im0/id 1 i gnd or v cc selects the transfer bus length for a parallel bus interface. gnd: 8-bit bus, vcc: 4-bit bus inputs the id of the device id code for a serial bus an d i2c bus interface. cs* 1 i mpu selects the hd66740: low: hd66740 is selected and can be accessed high: hd66740 is not selected and cannot be accessed must be fixed at gnd level when not in use. rs 1 i mpu selects the register for a parallel bus interface. low: instruction high: ram access must be fixed at gnd level when not in use. e/wr*/scl 1 i mpu for an 80-system parallel bus interface, serves as a write strobe signal and writes data at the low level. for a 68-system parallel bus interface, serves as an enable signal to activate data read/write operation. inputs the serial transfer clock for a serial interface. fetches data at the rising edge of a clock. rw/rd*/ sda 1i or i/o mpu for an 80-system parallel bus interface, serves as a write strobe signal and reads data at the low level. for a 68-system parallel bus interface, serves as a signal to select data read/write operation. low: write high: read serves as the bidirectional serial transfer data for a serial interface. sends/receives data.
hd66740 10 table 2 pin functional description (cont) signals number of pins i/o connected to functions db0Cdb7 8 i/o or i mpu serves as a bidirectional data bus for a parallel bus interface. for a 4-bit bus, data transfer uses db7-db4 must be fixed at gnd level when serial interface mod e is used. com1/80C com80/1 80 o l cd common output signals for graphics display: com1 t o com8 for the first line, com9 to com16 for the second line, com17 to com24 for the third line, com25 to com32 for the fourth line, and com73 to com80 for the 10th line. all the unused pins output unselected waveforms. in the sleep mode (slp = 1) o r standby mode (stb = 1), all pins output gnd level. the cms bit can change the shift direction of the common signal. for example, if cms = 0, com1/80 i s com1. if cms = 1, com1/80 is com80. note that the start position of the common output (the first line) is shifted by cn1Ccn0 bits. seg1/112C seg112/1 112 o l cd segment output signals for graphics display. in the sleep mode (slp = 1) or standby mode (stb = 1), all pins output gnd level. the sgs bit can change the shift direction of the segment signal. for example, if sgs = 0, seg1/112 i s seg1. if sgs = 1, seg1/112 is seg112. v1outCv5 out 5 i or o open or external bleeder-resistor used for output from the internal operational amplifier s when they are used (opoff = gnd); attach a capacitor to stabilize the output. when the amplifiers are not used (opoff = v cc ), v1 to v5 voltages can b e supplied to these pins externally. v lcd 3 power supply power supply for lcd drive. v lcd C gnd = 15 v max. v cc , gnd 12 power supply v cc : +1.8 v to +3.6 v; gnd (logic): 0 v osc1, osc2 2 i or o oscillation- resistor or clock for r-c oscillation using an external resistor, connect an external resistor. for external clock supply, input clock pulses to osc1. vci 5 i power supply inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. the boosting output voltage must not be larger than the absolute maximum ratings. must be left disconnected when the booster is not used. vlout 3 o v l c d pin/booster capacitance potential difference between vci and gnd is triple- to five-times-boosted and then output. magnitude of boost is selected by instruction.
hd66740 11 table 2 pin functional description (cont) signals number of pins i/o connected to functions c1+, c1C 8 booster capacitance external capacitance should be connected here for boosting. c2+, c2C 6 booster capacitance external capacitance should be connected here when using the triple or more booster. c3+, c3C 6 booster capacitance external capacitance should be connected here when using the quadruple and five-times booster. c4+, c4C 6 booster capacitance external capacitance should be connected here when using the five-times booster. reset* 1 i mpu or external r-c circuit reset pin. initializes the lsi when low. opoff 1 i v cc or gnd turns the internal operational amplifier off when opoff = v cc , and turns it on when opoff = gnd. if the amplifier is turned off (opoff = v cc ), v1 to v5 must be supplied to the v1out to v5out pins. vccdum 1 o input pins outputs the internal v cc level; shorting this pin sets th e adjacent input pin to the v cc level. gnddum 1 o input pins outputs the internal gnd level; shorting this pin sets the adjacent input pin to the gnd level. dummy 5 dummy pad. must be left disconnected. test 1 i gnd test pin. must be fixed at gnd level. vtest1 1 i gnd or v cc adjusts the driving capability of the internal operationa amplifier for the lcd. this signal enters the normal drive mode in the gnd side, and it enters the high- power drive mode in the v cc side. when the display quality is not sufficient, use the high-power drive mod e even though the power-consumption current is large. vtest2 1 test pin. must be left disconnected. vtest3 1 i v cc or gnd adjusts the driving capability of the internal operationa amplifier for the lcd. this signal enters the normal drive mode or high-power mode in the gnd side according to the vtest1 pin setting, and it enters th e low-power drive mode in the v cc side. use this sign a in the low-power mode so that the display quality is n o lowered.
hd66740 12 block function description system interface the hd66740 has six types of system interfaces, and a clock-synchronized serial, an i2c bus interface, a 68-system 4-bit/8-bit bus, and a 80-system 4-bit/8-bit bus. the interface mode is selected by the im2-0 pins. the hd66740 has two 8-bit registers: an instruction register (ir) and a data register (dr). the ir stores instruction codes, such as clear display, display control, and address information for the display character generator ram (cgram). the dr temporarily stores data to be written into the cgram. data written into the dr from the mpu is automatically written into the cgram by internal operation. when address information is written into the ir, data is read and then stored in the dr from the cgram by internal operation. data is read through the dr when reading from the ram, and the first read data is invalid and the second and the following data are normal. after reading, data in the cgram at the next address is sent to the dr for the next reading from the mpu. execution time for instruction excluding clear display is 0 clock cycle and instructions can be written in succession. table 3 register selection by rs and r/w bits r/w bit rs bit operations 0 0 write instructions to ir 10 - 0 1 dr write as an internal operation (dr to cgram) 1 1 dr read as an internal operation (cgram to dr) address counter (ac) the address counter (ac) assigns addresses to the cgram. when an address set instruction is written into the ir, the address information is sent from the ir to the ac. after writing into the cgram, the ac is automatically incremented by 1 (or decremented by 1). after reading from the data, the rdm bit automatically updates or does not update the ac. character generator ram (cgram) the cgram serves as a ram to store 112 x 80-dot bit pattern data in the graphics display mode. here, display patterns are directly written into cgram. for details, see the graphics display section. timing generator the timing generator generates timing signals for the operation of internal circuits such as the cgram. the ram read timing for display and internal operation timing by mpu access are generated separately to avoid interference with one another. this prevents flickering in areas other than the display area when writing data to the cgram, for example.
hd66740 13 oscillation circuit (osc) the hd66740 can provide r-c osc illation simply thr ough the add ition of an external oscillation-resistor between the osc1 and osc2 pins. the appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. clock pulses can also be supplied externally. since r-c osc illation stops during the sta ndby mode, current consumption can be reduced. for details, see the oscillation circuit section. liquid crystal display driver circuit the liquid crystal display driver circuit consists of 80 common signal drivers (com1 to com80) and 112 s e g m e n t s i gn a l d r i v e r s ( s e g 1 t o s e g 112 ) . w h e n t h e nu m b e r o f l i n e s a r e s e l e c t e d by a p r og r a m , t h e required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output unselected waveforms. graphics data is sent serially through a 112-bit shift register and latched when all needed data has arrived. the latched data then enables the segment signal drivers to generate drive waveform outputs. the shift direction of 112-bit data can be changed by the sgs bit. the shift direction for the common driver can also be changed by the cms bit by selecting an appropriate direction for the device mounting configuration. when display is off, or during the standby or sleep mode, all the above common and segment signal drivers output the gnd level, halting the display. booster (dc-dc converter) the booster generates triple, quadruple, or five-times voltage input to the vci pin. with this, both the internal logic units and lcd drivers can be controlled with a single power supply. boost output level from triple to five-times boost can be selected by software. for details, see the power supply for liquid crystal display drive section. v-pin voltage follower a voltage follower for each voltage level (v1 to v5) reduces current consumption by the lcd drive power supply circuit. no external resistors are required because of the internal bleeder-resistor, which generates different levels of lcd drive voltage. this internal bleeder-resistor can be software-specified from 1/4 bias to 1/10 bias, according to the liquid crystal display drive duty value. the voltage followers can be turned off while multiplexing drive is not being used. for details, see the power supply for liquid crystal display drive section. contrast adjuster the contrast adjuster can be used to adjust lcd contrast in 64 steps by varying the lcd drive voltage by software. this can be used to select an appropriate lcd brightness or to compensate for temperature.
hd66740 14 cgram address map table 4 relationship between display position and cgram address (1) db0 000 db1 db2 db3 db4 db5 db6 db7 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 06e 06f 06d06c 06b com1 com2 com3 com4 com5 com6 com7 com8 db0 080 db1 db2 db3 db4 db5 db6 db7 081 082 083 084 085 086 087 088 089 08a 08b 08c 08d 08e 08f 090 0ee 0ef0ed0ec0eb com9 com10 com11 com12 com13 com14 com15 com16 db0 100 db1 db7 101 102 103 104 105 106 107 108 109 10a 10b 10c 10d10e 10f 110 16e 16f16d16c16b com17 com18 com24 seg1/112 seg2/111 seg3/110 seg4/109 seg5/108 seg6/107 seg7/106 seg8/105 seg9/104 seg10/103 seg11/102 seg12/101 seg13/100 seg14/99 seg15/98 seg16/97 seg17/96 seg108/5 seg109/4 seg110/3 seg111/2 seg112/1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 00 00 00 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 000 00 00 00 00 0 00 00 00 00 00 00 0 0 0 0 0 0 00 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 000 00 000 00 00 0 0 0 0 0 0 0 0 00000 0 000 00000 0 000 000 0 00 00 0 0 0 0 0 0 0 00 0 0 0 00 0 00 (hex) (hex) (hex) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 db0 180 db1 db7 181 182 183 184 185 186 187 188 189 18a 18b 18c 18d 18e 18f 180 1ee 1ef1ed1ec1eb com25 com26 com32 00 0 1 0 1 1 0 1 1 1 00000 00 0 0000000000000000 00000 0 010 00 00 (hex) 0 0 0 000000 1 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 10 0 000000 00 0 00 0 000 00 0 1 1 1 1 1 1 1 1 0 0 10 1 1 1 00 0 0 00000000000000 0 1 0 0 1 1 1 1 1 1 1 1 00 0000000 00 00 00 0 0 0 0 00000000000 00 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 1 1 06f 06e 06d 06c 06b 06a 069 068 067 066 065 064 063 062 061 060 05f 001 000002003004 0ef 0ee 0ed0ec0eb 0ea 0e9 0e8 0e7 0e6 0e5 0e4 0e3 0e2 0e1 0e0 0df 081 080082083084 1ef 1ee 1ed1ec1eb 1ea 1e9 1e8 1e7 1e6 1e5 1e4 1e3 1e2 1e1 1e0 1df 181 180182183184 16f 16e 16d16c 16b 16a 169 168 167 166 165 164 163 162 161 160 15f 101 100102103104 db0 200 db1 db7 201 202 203 204 205 206 207 208 209 20a 20b 20c 20d 20e 20f 210 26e 26f26d26c26b com33 com34 com40 00 0 10 1 1 0 1 1 1 00000 00 0 0000000000000000 00000 0 010 00 00 (hex) 0 0 0 00000 00 0 00 00 00 0 26f 26e 26d 26c 26b 26a 269 268 267 266 265 264 263 262 261 260 25f 201 200202203204 sgs="0" sgs="1" segment driver address common segment sgs="0" sgs="1" address sgs="0" sgs="1" address sgs="0" sgs="1" address sgs="0" sgs="1" address notes: 1. a set bit in cgram data 1 corresponds to display selection (lit) and 0 to non-selection (unlit).
hd66740 15 table 5 relationship between display position and cgram address (2) 280 281 282 283 284 285 286 287 288 289 28a 28b 28c 28d 28e 28f 290 2ee 2ef 2ed2ec 2eb seg1/112 seg2/111 seg3/110 seg4/109 seg5/108 seg6/107 seg7/106 seg8/105 seg9/104 seg10/103 seg11/102 seg12/101 seg13/100 seg14/99 seg15/98 seg16/97 seg17/96 seg108/5 seg109/4 seg110/3 seg111/2 seg112/1 (hex) 2ef 2ee 2ed2ec2eb 2ea 2e9 2e8 2e7 2e6 2e5 2e4 2e3 2e2 2e1 2e0 2df 281 280282283284 db0 db1 db2 db3 db4 db5 db6 db7 com41 com42 com43 com44 com45 com46 com47 com48 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 00 00 0 00 0 000 0 0 0 0 0 1 1 0 0 0 00 00 0 0 0 1 1 1 1 1 1 0 0 000 0 1 1 00 00 0 1 10 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 00 1 0 0 0 0 00 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 db0 db1 db2 db3 db4 db5 db6 db7 com49 com50 com51 com52 com53 com54 com55 com56 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 00 00 0 00 0 000 0 0 0 0 0 0 0 0 0 0 00 00 0 0 0 1 0 0 1 1 1 0 0 0 00 0 1 1 0 1 1 1 1 1 10 0 0 1 10 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 00 01 10 0 1 0 1 1 1 1 0 0 1 1 1 0 0 0 0 00 0 0 1 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 00 1 0 0 0 0 00 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 db0 db1 db7 com57 com58 com64 0 1 1 1 10 0 1 00000 00 00 0 00 0 1 0 1 0 000 00 10 0 10 00 0 1 10 0 1 0 0 100 10 00 0 1 10 0 00 1 1 0 1 1 db0 db1 db7 com65 com66 com72 1 1 1 1 10 1 0 00000 10 00 00 0 0 1 1 1 0 000 10 0 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 00 00 00 0 1 10 0 00 1 1 0 1 1 0 300 301 302 303 304 305 306 307 308 309 30a 30b 30c 30d 30e 30f 310 36e 36f36d36c 36b (hex) 36f 36e 36d 36c 36b 36a 369 368 367 366 365 364 363 362 361 360 35f 301 300302303304 380 381 382 383 384 385 386 387 388 389 38a 38b 38c 38d 38e 38f 390 3ee 3ef3ed3ec 3eb (hex) 3ef 3ee 3ed3ec 3eb 3ea 3e9 3e8 3e7 3e6 3e5 3e4 3e3 3e2 3e1 3e0 3df 381 380382383384 400 401 402 403 404 405 406 407 408 409 40a 40b 40c 40d 40e 40f 410 46e 46f46d46c 46b (hex) 46f 46e 46d 46c 46b 46a 469 468 467 466 465 464 463 462 461 460 45f 401 400402403404 db0 db1 db7 com73 com74 com80 1 1 1 1 10 1 0 00000 10 00 00 0 0 1 1 1 0 000 10 0 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 00 00 00 0 1 10 0 00 1 1 0 1 1 480 481 482 483 484 485 486 487 488 489 48a 48b 48c 48d 48e 48f 490 4ee 4ef4ed4ec4eb (hex) 4ef 4ee 4ed4ec4eb 4ea 4e9 4e8 4e7 4e6 4e5 4e4 4e3 4e2 4e1 4e0 4df 481 480482483484 sgs="0" sgs="1" segment driver address sgs="0" sgs="1" address sgs="0" sgs="1" address sgs="0" sgs="1" address sgs="0" sgs="1" address common segment notes: 1. a set bit in cgram data 1 corresponds to display selection (lit) and 0 to non-selection (unlit).
hd66740 16 instructions outline only the instruction register (ir) and the data register (dr) of the hd66740 can be controlled by the mpu. before starting internal operation of the hd66740, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or mpus which operate at different speeds. the internal operation of the hd66740 is determined by signals sent from the mpu. these signals, which include the register selection signal (rs), the read/write signal (r/w), and the data bus signal (db0 to db7), make up the hd66740 instructions. there are four categories of instructions that: control the display control power management set internal ram addresses transfer data with the internal ram normally, instructions that perform data transfer with the internal ram are used the most. however, auto-incrementation by 1 (or auto-decrementation by 1) of internal hd66740 ram addresses after each data write can lighten the mpu program load. because instructions are executed in 0 cycle, instructions can be written in succession.
hd66740 17 instruction descriptions start oscillation the start oscillation instruction restarts the oscillator from the halt state in the sta ndby mode. after issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (see the standby mode section.) r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 00000011 figure 1 start oscillation instruction driver output control cms: selects the output shift direction of a common driver. when cms = "0", com1/80 shifts to com1, and com80/1 to com80. when cms = "1", com1/80 shifts to com80, and com80/1 to com1. output position of a common driver shifts depending on the cn1C0 bit se tting. for details, see the display on/off control section. sgs: selects the output shift direction of a segment driver. when sgs = "0", seg1/112 shifts to seg1, and seg112/1 to seg112. when sgs = "1", seg1/112 shifts seg112, and seg112/1 to seg1. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 0 0 0 1 cms sgs figure 2 driver output control instruction
hd66740 18 power control amp: when amp = 1, each voltage follower for v1 to v5 pins and the booster are turned on. when amp = 0, current consumption can be reduced while the display is not being used. slp: when slp = 1, the hd66740 enters the sleep mode, where the internal operations are halted except for the r-c oscillator, thus reducing current consumption. for details, see the sleep mode section. only the power control (amp, slp, and stb bits) instruction can be executed during the sleep mode. during the sleep mode, the other ram data and instructions cannot be updated although they are retained. stb: when stb = 1, the hd66740 enters the standby mode, where display operation completely stops, halting all the internal operations including the internal r-c oscillator. further, no external clock pulses are supplied. for details, see the standby mode section. only the following instructions can be executed during the standby mode. a. standby mode cancel (stb = 0) b. voltage follower circuit on/off (amp = 1/0) c. start oscillation during the standby mode, the other ram data and instructions may be lost. to prevent this, they must be set again after the standby mode is canceled. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 0 0 0 0 1 amp slp stb figure 3 power control instruction
hd66740 19 contrast control 1/2 sw: switches the bit configuration for the contrast control instruction. ct4Cct0: when sw = 0, they control the lcd drive voltage (potential difference between v1 and gnd) to adjust contrast. a 64-step adjustment is also possible by using the ct5 bit which are set in the entry mode register. for details, see the contrast adjuster section. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 000 10 sw ct4 ct3 bt1 bt0 (sw = 0) (sw = 1) 00 000 11 ct1 ct0 bs1 bs0 (sw = 0) (sw = 1) ct2 bs2 figure 4 contrast-control 1/2 instruction v lcd v1 v2 v3 v4 v5 vr r r r 0 r r - + - + - + - + - + gnd hd66740 gnd figure 5 contrast adjuster
hd66740 20 table 6 ct bits and variable resistor value of contrast adjuster ct set value ct5 ct4 ct3 ct2 ct1 ct0 variable resistor (vr) 000000 3.20 x r 000001 3.15 x r 000010 3.10 x r 000011 3.05 x r 000100 3.00 x r ? ? ? ? 011111 1.65 x r 100000 1.60 x r 100001 1.55 x r 100010 1.50 x r ? ? ? ? 111101 0.15 x r 111110 0.10 x r 111111 0.05 x r bt1-0: when sw = 1, they switch the output of v5out between triple, quadruple, and five-times boost. the liquid crystal display drive voltage level can be selected according to its drive duty ratio and bias. a lower amplification of the booster consumes less current. bs2-0: when sw = 1, they set the crystal display drive bias value within the range of 1/4 to 1/10 bias. the liquid crystal display drive bias value can be selected according to its drive duty ratio and voltage. for details, see the liquid crystal display drive bias selector section. table 7 bt bits and output level bt1 bt0 v5out output level 0 0 triple boost 0 1 quadruple boost 1 0 five-times boost 1 1 setting inhibited
hd66740 21 table 8 bs bits and lcd drive bias value bs2 bs1 bs0 liquid crystal display drive bias value 0 0 0 1/10 bias drive 0 0 1 1/9.5 bias drive 0 1 0 1/9 bias drive 0 1 1 1/8 bias drive 1 0 0 1/7 bias drive 1 0 1 1/6 bias drive 1 1 0 1/5 bias drive 1 1 1 1/4 bias drive
hd66740 22 entry mode rev: displays all graphics display sections with black-and-white reversal when sw = 0 and rev = 1. for details, see the reversed display function section. i/d: when sw = 0, increments (i/d = 1) or decrements (i/d = 0) the cgram address by 1 when a data is written into or read from the cgram. ct5: sets the most significant bit (ct5) for contrast adjustment when sw = 1. a 64-step adjustment is also possible by using the ct4Cct0 bits which are set in the contrast-control 1/2 instruction. rdm: when sw = 1 and rdm = 0, the rdm increments or decrements the address counter value according to the i/d bit setting after reading the data from the cgram. when rdm = 1, the address counter value is not updated after the data has been read from the cgram. the address counter value is used when the ram data is read, modified, and written. since the first read data is invalid, the read must be continuously done twice. after writing to the ram, the address counter value must be updated. r/w rs db7 db0db6 db5 db4 db3 db2 db1 00 001 00 i/d rdm (sw = 0) (sw = 1) rev ct5 0 1 figure 6 entry mode set instruction
hd66740 23 display on/off control d: display is on when sw = 0 and d = 1 and off when d = 0. when off, the display data remains in the ddram or cgram, and can be displayed instantly by setting d = 1. when d is 0, the display is off with the seg1 to seg112 outputs and com1 to com80 outputs set to the gnd level. because of this, the hd66740 can control charging current for the lcd with ac driving. dl10: when sw = 0, dl10 can be set. when dl10 = 1, the 10th line is displayed at double height. dl9Cdl7: when sw = 1, dl9Cdl7 can be set. double-height display is specified for any display line. when dl7 = 1, the seventh line is displayed at double height. double-height display is used for the eighth line when dl8 = 1 and for the ninth line when dl9 = 1. for double-height display for the first to the sixth lines, control them by using dl1Cdl6 bits in the display-line control instruction. r/w rs db7 db0db6 db5 db4 db3 db2 db1 00 001 10 dl10 dl8 dl7 (sw = 0) (sw = 1) d dl9 0 figure 7 display on/off control instruction
hd66740 24 display line control nl3-0: set nl2Cnl0 bits when sw = 0, and the nl3 bit when sw = 1 to specify the display lines. display lines change the liquid crystal display drive duty ratio. cgram address mapping does not depend on the number of display lines. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 00111 nl1 nl0nl2 cn0 nl3cn1 (sw = 0) (sw = 1) figure 8 display-line control instruction table 9 nl bits and display lines nl3 nl2 nl1 nl0 graphics display lcd drive duty common driver used 0000 112 x 8 dots 1/8 duty com1Ccom8 0001 112 x 16 dots 1/16 duty com1Ccom16 0010 112 x 24 dots 1/24 duty com1Ccom24 0011 112 x 32 dots 1/32 duty com1Ccom32 0100 112 x 40 dots 1/40 duty com1Ccom40 0101 112 x 48 dots 1/48 duty com1Ccom48 0110 112 x 56 dots 1/56 duty com1Ccom56 0111 112 x 64 dots 1/64 duty com1Ccom64 1000 112 x 72 dots 1/72 duty com1Ccom72 1001 112 x 80 dots 1/80 duty com1Ccom80 cn1Ccn0: set cn1Ccn0 bits when sw = 1. when cn1C0 = 01, the display position is shifted by 16 dots below and display starts from com17. when the liquid crystal is driven at low duty in the system wait state, it can display partially at the center of the screen. for details, see the partial-display-on function section. when cn1Ccn0 = 10, the display position is shifted by 8 dots above and second-line display starts from com1. the 8 dots of the first line are moved to the lowest edge of the display screen. the output position of the lowest edge depends on the drive duty setting. in vertical smooth scrolling, ps1Cps0 bits can selectively fixed-display only the first to the third lines. combining these functions enables the fixed display of one line of the lowest edge. for details, see the partial smooth scroll display function section.
hd66740 25 table 10 common driver pin function common driver pin function cn 1C0 = 00 (normal output) cn 1C0 = 01 (center output) cn1C0 = 10 (lowest-edge output) common driver pin cms = 0 cms = 1 cms = 0 cms = 1 cms = 0 cms = 1 com1/80 com1 com80 com65 com64 com9 com8 com2/79 com2 com79 com66 com63 com10 com7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com7/72 com7 com74 com71 com58 com15 com2 com8/73 com8 com73 com72 com57 com16 com1 com9/72 com9 com72 com73 com56 com17 com80 com10/71 com10 com71 com74 com55 com18 com79 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com15/66 com15 com66 com79 com50 com23 com73 com16/65 com16 com65 com80 com49 com24 com72 com17/64 com17 com64 com1 com48 com25 com71 com18/63 com18 com63 com2 com47 com26 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com66 com24/57 com24 com57 com8 com41 com32 com65 com25/56 com25 com56 com9 com40 com33 com64 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com32/49 com32 com49 com16 com33 com40 com57 com33/48 com33 com48 com17 com32 com41 com56 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com40/41 com40 com41 com24 com25 com48 com49 com41/40 com41 com40 com25 com24 com49 com48 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com48/33 com48 com33 com32 com17 com56 com41 com49/32 com49 com32 com33 com16 com57 com40 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com56/25 com56 com25 com40 com9 com64 com33 com57/24 com57 com24 com41 com8 com65 com32 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com64/17 com64 com17 com48 com1 com72 com25 com65/16 com65 com16 com49 com80 com73 com24 ? ? ? ? ? ? ? ? ? ? ? ? ? ? com72/9 com72 com9 com56 com73 com80 com17 com73/8 com73 com8 com57 com72 com1 com16 ? ? ? ? ? ? ? ? ? ? com2 com15 com79/2 com79 com2 com63 com66 ? ? ? ? com80/1 com80 com1 com64 com65 com8 com9 double-height display control dl3-1: can be specified when sw = 0. specify the double-height display for any line. when dl1 = 1, the first line is displayed at double height. when dl2 = 1, the second line is displayed at double
hd66740 26 height. when dl3 = 1, the third line is displayed at double height. double-height display of multiple lines is possible. for details, see the double-height display section. dl6-4: can be specified when sw = 1. specify the double-height display for any line. when dl4 = 1, the fourth line is displayed at double height. when dl5 = 1, the fifth line is displayed at double height. when dl6 = 1, the sixth line is displayed at double height. for the seventh to 10th lines, control double-height display by using the dl7Cdl10 bits in the display-line control instruction. for details, see the double-height display section. r/w rs db7 db0db6 db5 db4 db3 db2 db1 00 01000 dl2 dl1dl3 dl5 dl4 dl6 (sw = 0) (sw = 1) figure 9 double-height display control instruction
hd66740 27 vertical scroll control 1/2 sn3-0: set sn2 to sn0 bits when sw = 0. set the sn3 bit when sw = 1. specify the display start line output from com1. because the cgram is assigned a 10-line display area, the data is displayed sequentially from the first line to the 10th line then repeated from the first line again. in partial smooth scrolling, these bits specify the display start line for the next line of the fixed-display line. for details, see the partial smooth scroll display function section. sl2C0: select the top raster-row to be displayed (display-start raster-row) in the display-start line specified by sn2 to sn0. any raster-row from the first to eighth can be selected (table 12). this function is used to achieve vertical smooth scrolling together with sn2 to sn0. for details, see the vertical smooth scroll section. r/w rs db7 db0db6 db5 db4 db3 db2 db1 00 010 01 sn1 sn0 <0> sn3 (sw = 0) (sw = 1) sn2 <0> 00 010 10 sl1 sl0 ps1 ps0 (sw = 0) (sw = 1) sl2 <0> figure 10 vertical scroll control 1/2 instruction table 11 sn bits and display-start lines sn3 sn2 sn1 sn0 display-start line 0 0 0 0 1st line 0 0 0 1 2nd line 0 0 1 0 3rd line 0 0 1 1 4th line 0 1 0 0 5th line 0 1 0 1 6th line 0 1 1 0 7th line 0 1 1 1 8th line 1 0 0 0 9th line 1 0 0 1 10th line
hd66740 28 table 12 sl bits and display-start raster-row sl2 sl1 sl0 display-start raster-row 0 0 0 1st raster-row 0 0 1 2nd raster-row 0 1 0 3rd raster-row 0 1 1 4th raster-row 1 0 0 5th raster-row 1 0 1 6th raster-row 1 1 0 7th raster-row 1 1 1 8th raster-row ps1C0: specify ps1 to ps0 bits when sw = 1. when ps1C0 = 01, only the first line is fixed-displayed in vertical smooth scrolling, and the other display lines are smooth-scrolled. when ps1C0 = 10, the first and second lines are fixed-displayed. when ps1C0 = 11, the first to third lines are fixed-displayed. for details, see the partial smooth scroll display function section. lcd-driving-pattern control b/c: when sw=1 and b/c=0, a b-pattern waveform is generated and alternates in every frame for lcd drivin. when b/c=1, a c-pattern wavefrom is generated and alternates (n-raster-row reversed ac drive) in each raster-row specified by bits eor and nw4-nw0 in the lcd-driving-waveform control register. for details, see the n-raster-row reversed ac drive section. dcc: when sw=1 and dcc=0, a booster operates with the 64-divided clock of the operating frequency. when dcc=1, the booster operates with the 32-divided clock. when the booster operates with the 64-divided clock, current consumptionin the booster is low, but boosting ability is weak. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 01110 (sw = 1) dcc b/c 0 figure 10a lcd-driving-waveform control instruction lcd-driving-waveform control eor: when the c-pattern waveform is set (b/c = 1) and sw = 1 and eor = 1, the odd/even frame-select signals and the n-raster-row reversed signals are eored for alternating drive. eor is used when the lcd is not alternated by combining the set values of the lcd drive duty ratio and n raster-row. for details, see the n-raster-row reversed ac drive section. nw4C0: specify the number of raster-rows n that will alternate at the c-pattern waveform setting (b/c = 1). nw4Cnw0 alternate in every set value + 1 raster-row, and the first to the 32nd raster-rows can be selected. when sw = 0, bits nw2, nw1, and nw0 can be set. when sw = 1, bits nw4 and nw3 can be set.
hd66740 29 r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 01111 nw4 nw3eor nw1 nw0nw2 (sw = 0) (sw = 1) figure 11 lcd-driving-waveform control instruction
hd66740 30 ram address set ad10-0: initially set ram addresses to the address c ounter (ac). once the ram data is written, the ac is automatically updated according to the i/d bit. this allows consecutive accesses without resetting addresses. once the ram data is read, the ac is automatically updated according to the i/d bit when rdm = 0, and not updated when rdm = 1. set rdm to 1 when read, modify, and write are done in every one-byte data. ram address setting is not allowed in the sleep mode or standby mode. r/w rs db7 db0 00 db6 db5 db4 db3 db2 db1 1 0 ad7 ad6 00 1 1 ad2 ad1 ad0 ad8 ad3 ad9 ad4ad5 ad10 1 figure 12 ram address set instruction table 13 ad bits and cgram settings ad10Cad0 cgram setting "000"hC"06f"h bit map data for com1 to com8 "080"hC"0ef"h bit map data for com9 to com16 "100"hC"16f"h bit map data for com17 to com24 "180"hC"1ef"h bit map data for com25 to com32 "200"hC"26f"h bit map data for com33 to com40 "280"hC"2ef"h bit map data for com41 to com48 "300"hC"36f"h bit map data for com49 to com56 "380"hC"3ef"h bit map data for com57 to com64 "400"hC"46f"h bit map data for com65 to com72 "480"hC"4ef"h bit map data for com73 to com80 write data to ram wd7-0 : write 8-bit data to the cgram. after a write, the address is automatically incremented or decremented by 1 according to the i/d bit setting. during the sleep and standby modes, the cgram cannot be accessed. r/w rs db7 db0 01 db6 db5 db4 db3 db2 db1 wd7 wd6 wd5 wd4 wd3 wd2 wd1 wd0 figure 13 write data to ram instruction
hd66740 31 read data from ram rd7-0 : read 8-bit data from the cgram. in the parallel bus interface mode, the first-byte data read will be invalid immediately after the ram address set, and the consecutive second-byte data w ill be read normally. in the serial interface mode or i2c bus interface mode, two bytes will be invalid immediately after the start byte, and the consecutive third-byte data will be read normally. for details, see the serial data transfer section. after a ram read, when rdm = 0, the address is automatically incremented or decremented by 1 according to the i/d bit. when rdm = 1, the address is not updated. r/w rs db7 db0 11 db6 db5 db4 db3 db2 db1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 figure 14 read data from ram instruction address: n set dummy read (invalid data) read (data of address n) first byte second byte i) parallel bus interface mode address: n set dummy read (invalid data) read (data of address n) first byte third byte ii) serial interface mode start byte start byte dummy read (invalid data) second byte address: n 1 (rdm = 0) address: n (rdm = 1) address: n 1 (rdm = 0) address: n (rdm = 1) figure 15 ram read sequence
hd66740 32 table 14 instruction list register code execu- tion name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle start oscillation 0000 000 01 1 starts the oscillation standby mode. driver output control 0000 000 1cmssgs selects the common driver shift direction (cms) and segment driver shift direction (sgs). 0 power control 0000 001 ampslpstb turns on lcd power supply (amp), and sets the sleep mode (slp) and standby mode (stb). 0 contrast control 1 0000 010 swct4ct3 sets the register selection (sw) or upper contrast adjustment bits (ct4-3). 0 bt1 bt0 sets the register selection (sw) or boost level (bt1/0). 0 contrast control 2 0000 011 ct2ct1ct0 sets the lower contrast adjustment bits (ct2-0). 0 bs2 bs1 bs0 sets the lcd bias value (bs2-0). 0 entry mode set 0000 100 revi/d1 sets the black-and-white reversal (rev) and address update direction after ram access (i/d). 0 ct5 rdm 0 sets the higher contrast adjustment bit (ct5) and read modify write (rdm). 0
hd66740 33 table 14 instruction list (cont) register code execu- tion name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle display on/off control 0000 110 d dl10 0 sets display on (d) and double-height display line (dl10). 0 dl9 dl8 dl7 specifies double-height display lines (dl9Cdl7). 0 display line control 0000 111 nl2nl1nl0 sets the number of display lines (nl2-0). 0 cn1 cn0 nl3 specifies centering (cn1C0) or the number of display lines (nl3). 0 double-height display control 0001 000 dl3dl2dl1 specifies double-height display lines (dl3-1). 0 dl6 dl5 dl4 specifies double-height display lines (dl6C4). 0 vertical scroll control 1 0001 001 sn2sn1sn0 sets the display-start line (sn2-0). 0 <0> <0> sn3 sets the display-start line (sn3). 0 vertical scroll control 2 0001 010 sl2sl1sl0 sets the display-start raster- row (sl2-0). 0 <0> ps1 ps0 sets the partial scroll (ps1C0). 0
hd66740 34 table 14 instruction list (cont) register code execu- tion name r/w rs db7 db6 db5 db4 db3 db2 db1 db0 description cycle lcd-driving- pattern control 0001 110 0dccb/c selects the boosting cycle (dcc) or lcd drive ac waveform (b/c) 0 lcd-driving- waveform control 0001 111 nw2nw1nw0 sets the number of n-raster- rows (nw2C0) in c-pattern ac drive. 0 eor nw4 nw3 sets the eor output (eor) or the number of n-raster- rows (nw4C3) in c-pattern ac drive. 0 ram address set (upper bits) 0010 1 ad10C6 (upper bits) initially sets the upper addresses of the ram to the address counter (ac). 0 ram address set (lower bits) 0011 ad5-0 (lower bits) initially sets the lower addresses of the ram to the ac. 0 write data to ram 0 1 write data writes data to cgram. 0 read data from ram 1 1 read data reads data from cgram. 0 notes: 1. the upper column of each register can be set when sw = 0. the lower column can be set when sw = 1.
hd66740 35 bit definition: cms = 0: com1/80 => com1 sgs = 0: seg1/112 => seg1 amp = 1: operational amplifier and booster circuit on slp = 1: sleep mode stb = 1: standby mode sw = 0: upper register setting sw = 1: lower register setting ct5-0: contrast adjustment bt1-0: boost level selection (00: triple, 01: quadruple, 10: five-times) bs2-0: lcd drive bias selection rev = 0: normal display rev = 1: black-and-white reversed display of the graphics display id = 1: address increment id = 0: address decrement rdm = 1: read, modify, and write mode (not automatically update the address counter after reading) d = 1: display on nl3-0: display line setting (0000: 1/8 duty ratio, 0001: 1/16 duty ratio, 0010: 1/24 duty ratio, 0011: 1/32 duty ratio, 0100: 1/40 duty ratio, 0101: 1/48 duty ratio, 0110: 1/56 duty ratio, 0111: 1/64 duty ratio, 1000: 1/72 duty ratio, 1001: 1/80 duty ratio) dl1-10: double-height line specifications (dl1: 1st line, dl2: 2nd line, dl3: 3rd line, dl4: 4th line, dl5: 5th line, dl6: 6th line, dl7: 7th line, dl8: 8th line, dl9: 9th line, dl10: 10th line) sn3-0: display-start line (0000: 1st line, 0001: 2nd line, 0010: 3rd line, 0011: 4th line, 0100: 5th line, 0101: 6th line, 0110: 7th line, 0111: 8th line, 1000: 9th line, 1001: 10th line) sl2-0: display-start raster-row specifications (000: 1st raster-row...111: 8th raster-row) cn1C0 centering specifications (00: no centering, 01: 16-dot shift below, 10: 8-dot shift above) b/c = 0: b-pattern waveform drive b/c = 1: c-pattern waveform drive eor = 1: eor alternating drive at c-pattern waveform nw4C0: reversed number of n raster-rows at c-pattern waveform drive (alternating with the set value + one raster-row) dcc = 0: boosted at 1/64-divided clock dcc = 1: boosted at 1/32-divided clock ad10-0: cgram address set (cgram: 000h-4efh)
hd66740 36 reset function the hd66740 is internally initialized by reset input. the reset input must be held for at least 1 ms. instruction set initialization: 1. start oscillation executed 2. driver output control (sgs = 0, cms = 0) 3. power control (amp = 0: lcd power off, slp = 0: sleep mode off, stb = 0: standby mode off) 4. three times boost (bt1/0 = 00), 1/10 bias drive (bs2/1/0 = 000), weak contrast (ct5-0 = 00000) 5. entry mode set (rev = 0: normal display, i/d = 1: increment by 1, rdm = 0: automatically update after reading) 6. display on/off control (d = 0: display off, cen = 0: normal position) 7. display line control (nl3/2/1/0 = 1001: 1/80 duty ratio) 8. double-height display off (dl10C1 = 0000000000) 9. vertical scroll control (sn3/2/1/0 = 0000: first line displayed at the top, sl2/1/0: first raster-row displayed at the top of the first line, ps1/0 = 00: partial scroll off) 10. 1/64-divided clock boost (dcc = 0) 11. b-pattern waveform ac drive (b/c = 0, eor = 0, nw4/3/2/1/0 = 00000) ram data initialization: 1. cgram this is not automatically initialized by reset input but must be initialized by software while display is off (d = 0). output pin initialization: 1. lcd driver output pins (seg/com): outputs gnd level 2. booster output pins (vlout): outputs gnd level 3. oscillator output pin (osc2): outputs oscillation signal
hd66740 37 serial data transfer (clock synchronized serial interface) setting the im1 and im2 pins (interface mode pins) to the gnd level allows standard clock-synchronized serial data transfer, using the chip select line (cs*), serial data line (sda), and serial transfer clock line (scl). for a serial interface, the im0/id pin function uses an id pin. the hd66740 initiates serial data transfer by transferring the start byte at the falling edge of cs* input. it ends serial data transfer at the rising edge of cs* input. the hd66740 is selected when the 6-bit chip address in the start byte transferred from the transmi tting device matches the 6-bit device identification code assigned to the hd66740. the hd66740, when selected, receives the subsequent data string. the least significant bit of the identification code can be determined by the id pin. the five upper bits must be 01110. two different chip addresses must be assigned to a single hd66740 because the seventh bit of the start byte is used as a register select bit (rs): that is, when rs = 0, an instruction can be issued, and when rs = 1, data can be written to or read from ram. read or write is selected according to the eighth bit of the start byte (r/w bit) as shown in table 16. after receiving the start byte, the hd66740 receives or trans mits the subsequent data byte-by-byte. the data is transferred with the msb first. two bytes of ram read data after the start byte are invalid. the hd66740 starts to read correct ram data from the third byte. table 15 start byte format transfer bit s 1 2 3 4 5 6 7 8 start byte format transfer start device id code rs r/w 011 10id note: id bit is selected by the im0/id pin. table 16 rs and r/w bit function rs r/w function 0 0 writes instruction 01 - 1 0 writes ram data 1 1 reads ram data
hd66740 38 a) basic data-transfer timing through clock-synchronized serial bus interface start byte instruction, ram data scl (input) cs* (input) transfer start transfer end start byte instruction 1 execution time scl (input) b) consecutive data-transfer timing through clock-synchronized serial bus interface 1 2 3 4 5 6 7 8 9 101112 131415 16 17 1819 instruction 1 instruction 2 20 21 22 23 24 25 26 27 28 29 30 31 32 instruction 2 execution time instruction 3 start end cs* (input) sda (input/ output) sda (input/ output) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 db7 db6 db5 db4 r/w device id code id rs db3 db2 db1 db0 msb rs "1" r/w "1" "0" "1" "0" lsb start byte rs = 1, r/w = 1 scl (input) c) ram data read-transfer timing 1 2 3 4 5 6 7 8 9 101112 131415 16 17 1819 dummy read 1 dummy read 2 20 21 22 23 24 25 26 27 28 29 30 31 32 ram data read 1 start end cs* (input) sda (input/ output) note: when instruciton 1 is a clear display instruction, adjust the transfer rate so that the 8th bit of instruction 2 is transferred after execution of the clear display instruction. note: two bytes of the ram read data after the start byte are invalid. the hd66740 starts to read the correct ram data from the third byte. figure 16 clock-synchronized serial interface timing sequence
hd66740 39 serial data transfer (i2c bus interface) setting the im2=vcc and im1=gnd level allows i2c bus interface, using the serial data line (sda) and serial transfer clock line (scl). for the i2c bus interface, the im0/id pin function uses an id pin. the hd66740w is initiated serial data transfer by transferring the first byte when a high scl level at the falling edge of the sda input is sampled; it ends serial data transfer when a high scl level at the rising edge of the sda input is sampled. table 16-a illustrates the start byte of i2c bus interface data and figure 16-a and 16-b show the i2c bus interface timing sequence. the hd66740w is selected when the higher 6-bit slave address in the first byte transferred from the master device match the 6-bits device identification code assigned to the hd66740w. the hd66740w, when selected, receive the subsequent data string. the lower 1-bit of the device identification code can be determined by the id pin; select an appropriate code that is not assigned to any other slave device. the upper five bits are fixed to 01110. one slave address is assigned to a single hd66740w. the ninth bit of the first byte is a receive-data acknowledge bit (ack). when the received slave address matches the device id code, hd66740w pulls down the ack bit to a low level. therefore, the ack output buffer is an open-drain structure, only allowing low-level output. however, the ack bit is undermined immediately after power-on; make sure to initialize the lsi using the reset* input. after identifying the address in the first byte, the hd66740w receives the subsequent data as an hd66740w instruction or as ram data. having received 8-bit data normally, hd66740w pulls down the ninth bit (ack) to a low level. the instruction or ram data is 8-bits data format. two bytes of ram read data after the start byte are invalid. the hd66740w start to read correct ram data from third byte. table 16-a start byte format transfer bit s 1 2 3 4 5 6 7 8 9 start byte format transfer start device id code rs r/w ack 01110id note: id bit is selected by the im0/id pin. table 16-b rs and r/w bit function rs r/w function 0 0 writes instruction 01 - 1 0 writes ram data 1 1 reads ram data
hd66740 40 a) basic data-receive timing through the i2c bus interface 123456789101112131415161718 scl (input) sda (input/ output) "0" "1" "1" "1" "0" "0"id rs ack d7 d6 d5 d4 d3 d2 d1 d0 ack transfer start transfer end rs rw device id code acknowledge acknowledgestart byte instruction / ram data b) consecutive data-receive timing through the i2c bus interface 123456789101112131415161718192021222324252627 scl sda transfer start transfer end 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 start byte instruction or ram write instruction or ram write instruction or ram write instruction or ram write ack ack ack ack ack p s instruction / ram write execution. instruction / ram write execution. instruction / ram write execution. instruction / ram write execution. note: - start byte should be transfered just after start (s). figure 16-a i2c bus interface data-receive sequence a) basic data-send timing through the i2c bus interface 123456789101112131415161718 scl (input) sda (input/ output) "0" "1" "1" "1" "0" "1""1"id ack d7 d6 d5 d4 d3 d2 d1 d0 ack transfer start transfer end rs rw device id code acknowledge acknowledgestart byte ram read b) consecutive data-send timing through the i2c bus interface scl sda transfer start transfer end start byte dummy read (1 byte) ram data read ram data read ram data read ack ack ack ack ack p s note: - start byte should be transfered just after start (s). figure 16-b i2c bus interface data-send sequence
hd66740 41 parallel data transfer 8-bit bus interface setting the im2/1/0 (interface mode) to the gnd/vcc/gnd level allows e-clock-synchronized 8-bit parallel data transfer. setting the im2/1/0 (interface mode) to the vcc/vcc/gnd level allows 80- system 8-bit parallel data transfer. when the number of buses or the mounting area is limited, use a 4- bit bus interface or serial data transfer. c0 c1 c2 a0?7 e/wr* rs r/w / rd* (cs*) db0?b7 h8/325 hd66740 8 *interface via i/o port figure 17 interface to 8-bit microcomputer 4-bit bus interface setting the im2/1/0 (interface mode) to the gnd/vcc/vcc level allows e-clock-synchronized 4-bit parallel data transfer using pins db7-db4. setting the im2/1/0 (interface mode) to the vcc/vcc/vcc level allows 80-system 4-bit parallel data transfer. the 8-bit instructions and ram data are divided into four upper/lower bits and the transfer starts from the upper four bits. note: transfer synchronization function for a 4-bit bus interface the hd66740 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 4-bit data transfer in the 4-bit bus interface. noise causing transfer mismatch between the four upper and lower bits can be corrected by a reset triggered by consecutively writing a 0000 instruction four times. the next transfer starts from the upper four bits. executing synchronization function periodically can recover any runaway in the display system. "0000" "0000" "0000" "0000" rs r/w e db7 db4 upper lower (4-bit transfer synchronization) (1) (2) (3) (4) upper/ lower figure 18 4-bit transfer synchronization
hd66740 42 oscillation circuit the hd66740 can either be supplied with operating pulses externally (external clock mode) or osc illate using an internal r-c oscillator with an external oscillator-resistor (external resistor oscillation mode). note that in r-c oscillation, the oscillation frequency is changed according to the internal capacitance value, the external resistance value, or operating power-supply voltage. insert the dumping registance of about 1.5k w to prevent malfunctions caused by over-shoot or under-shoot noise in the external clock mode. 1) external clock mode 2) external resistor oscillation mode osc1 osc1 osc2 clock insert the dumping resistance. (80 khz) rf the oscillator frequency can be adjusted by oscillator resistor (rf). if rf is increased or power supply voltage is decreased, the oscillation frequency decreases. for the relationship between rf resistor value and oscillation frequency, see the electric characteristics notes section. hd66740 hd66740 1.5 k figure 19 oscillation circuits table 17 relationship between drive duty ratio and frame frequency (fosc = 75 khz) display mode 1-line dis- play 2-line dis- play 3-line dis- play 4-line dis- play 5-line dis- play 6-line dis- play 7-line dis- play 8-line dis- play 9-line dis- play 10-line dis- play set value for nl3C0 lcd drive 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 multiplexing duty ratio 1/8 1/16 1/24 1/32 1/40 1/48 1/56 1/64 1/72 1/80 drive bias (recommend- ed value) 1/4 1/5 1/6 1/6 1/7 1/8 1/8 1/9 1/9.5 1/10 frame frequency 73 hz 73 hz 73 hz 73 hz 72 hz 74 hz 74 hz 73 hz 65 hz 59 hz one-frame frequency 1,024 1,024 1,032 1,024 1,040 1,008 1,008 1,024 1,152 1,280 note: if the frame frequency is low and the display flickers, increase the oscillation frequency (fosc). particularly in the 9-line display and 10-line display modes, note that the frame frequency is lowered.
hd66740 43 1 2 3 4 79 80 1 2 3 79 8 0 v1 v2 v5 gnd com1 v2 v5 gnd com2 1 frame 1 frame v1 v2 v5 gnd com79 v1 v2 v5 gnd com80 v1 figure 20 lcd drive output waveform (b-pattern ac drive with 1/80 multiplexing duty ratio)
hd66740 44 n-raster-row reversed ac drive the hd66740 supports not only the lcd reversed ac drive in a one-frame unit (b-pattern waveform) but also the n-raster-row reversed ac drive which alternates in an n-raster-row unit from one to 32 raster-rows (c-pattern waveform). when a problem affecting display quality occurs, such as crosstalk at high-duty driving of more than five lines (1/40 duty), the n-raster-row reversed ac drive (c-pattern waveform) can improve the quality. determine the number of raster-rows n (nw bit set value + 1) for alternating after confirmation of the display quality with the actual lcd panel. however, if the number of ac raster-rows is reduced, the lcd alternating frequency becomes high. because of this, the charge or discharge current is increased in the lcd cells. 1 2 3 4 5 6 7 8 9 10 11 12 13 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 79 80 1 2 3 b-pattern waveform drive ?1/80 duty 1 frame 1 frame c-pattern waveform drive ?1/80 duty ?11-raster-row reversal ?without eors c-pattern waveform drive ?1/80 duty ?11-raster-row reversal ?with eors note: specify the number of ac drive raster-rows and the necessity of eor so that the dc bias is not generated for the liquid crystal. figure 21 example of an ac signal under n-raster-row reversed ac drive
hd66740 45 liquid crystal display voltage generator when external power supply and internal operational amplifiers are used to supply lcd drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in figure 22. here, contrast can be adjusted by software through the ct bits of the contrast adjustment register. the hd66740 incorporates a voltage-follower operational amplifier for each v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. thus, potential differences between v lcd and v1 and between v5 and gnd must be 0.4 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.1 f to 0.5 f between each internal operational amplifier v1out to v5out output and gnd and stabilize the output level of the operational amplifier. c1+ v lcd v lcd vr r 0 r r r - + - + - + - + - + gnd booster opoff = gnd r hd66740 v1out + v2out v3out v4out v5out + + + + lcd driver seg1 to seg112 com1 to com80 v1 v3 v4 v2 v5 gnd vci c1- c2+ c2- vlout 0.1 f to 0.5 f gnd c3+ c3- c4+ c4- figure 22 external power supply circuit for lcd drive voltage generation
hd66740 46 when an internal booster and internal operational amplifiers are used to supply lcd drive voltage using the internal booster, circuits should be connected as shown in figure 23. here, contrast can be adjusted through the ct bits of the contrast control instruction. temperature can be compensated either through the ct bits or by controlling the reference voltage for the booster (vci pin) using a thermistor. note that vci is both a reference voltage and power supply for the booster. the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. in this case, vci must be equal to or smaller than the v cc level. the hd66740 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder-resistors, which generate different liquid-crystal drive voltages. thus, the potential differences between v lcd and v1 and between v5 and gnd must be 0.4 v or higher. note that the opoff pin must be grounded when using the operational amplifiers. place a capacitor of about 0.1 f to 0.5 f between each internal operational amplifier v1out to v5out output and gnd and stabilize the output level of the operational amplifier.
hd66740 47 v lcd vr r 0 r r r - + - + - + - + - + gnd c1+ c1- vci + 1 f 1 f vlout gnd + c2+ c2- + booster opoff = gnd r hd66740 v1out + v2out v3out v4out v5out + + + + lcd driver seg1 to seg112 com1 to com80 v1 v3 v4 v2 v5 gnd 0.1 f to 0.5 f gnd vci c3+ c3- + c3+ c3- + 1 f 1 f 1 f notes: 1. the reference voltage input (vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating for the liquid-crystal power supply voltage (17 v). particularly, vci must be 3.3 v or less for five-times boosting. 2. vci is both a reference voltage and power supply for the booster; connect it to vcc directly or combine it with a transistor so that sufficient current can be obtained. 3. polarized capacitors must be connected correctly. 4. circuits for temperature compensation should be based on the sample circuit in figure 24. figure 23 internal booster for lcd drive voltage generation vcc thermistor gnd tr vcc vci hd66740 figure 24 temperature compensation circuit
hd66740 48 notes on using internal operational amplifier the hd66740 has a low-current-consumption-type operational amplifier. when a low-voltage supply is used, particularly at low temperatures near C20 c, the current in the operational amplifier is reduced. therefore, depending on the specifications or display pattern of the lcd panel used, screen quality may be poor or the lcd panel may not operate at all. for the operational specifications of the lcd panel, one must consider the drive condition (setting of the vtest pin) or the peripheral circuits of the lcd panel in conjunction with the power-supply voltage. pin condition for hd66740 (setting vtest pin): 1. when the power-supply voltage is vcc 3 2.5 v (i.e., the current in the operational amplifier is sufficient), leave the vtest pin open (disconnected). 2. when the power-supply voltage is vcc < 2.5 v (i.e., the current is reduced in the operational amplifier at low temperature), 1.2 to 1.3 v should be input to the vtest pin. the following table and figure correspond to inputs of 1.2 to 1.3 v to the vtest pin. when higher lcd drive current is required due to the characteristics of the lcd panel, check the screen quality and current consumption, adjust the resistance values (r1 and r2), and increase the vtest pin voltage. (this is also valid when vcc 3 2.5 v.) gnd vcc to vtest pin vtest = 1.2 to 1.3v r1 r2 figure 24-a circuit to for generating vtest pin voltage table 17-a settings to generate vtest pin voltage vcc r1 r2 vtest (vtest pin voltage) 2.4 v 270 k w 330 k w 1.23 v 2.0 v 220 k w 360 k w 1.22 v 1.8 v 180 k w 390 k w 1.22 v
hd66740 49 countermeasures for screen quality when using on-chip operational amplifier the hd66740 is an on-chip lcd driver that has an lcd power supply for high duty. screen quality is affected by the load current of the high-duty lcd panel used. when the bias (1/10 bias, 1/9.5 bias, 1/9 bias, etc.) is high and the displayed pattern is completely or almost completely white, the white sections may appear dark. if this happens, execute the following countermeasures to improve screen quality. (1) after the change in the v4out/v3out level is verified, insert about 1 m w between v4out and gnd or vlcd and v3out and then adjust the screen quality (see the following figures). by inserting resistance, the current consumption increases as much as the boosting factor of the resistance current. adjust the resistance after checking the screen quality and the increase in current consumption. (2) decrease the drive bias and use the new bias level after verifying that the potential differences between v4out and gnd or vlcd and v3out are sufficient. gnd vlcd driver vbn fixed current source rv4 c v4out figure 24-b countermeasure for v4out output gnd vlcd driver vbp fixed current source rv3 c v3out figure 24-c countermeasure for v3out output note: the actual lcd drive voltage-vlcd used must not exceed 15.0 v, and the absolute rating must not exceed 16.0 v.
hd66740 50 switching the boosting multiplying factor instruction bits (bt1/0 bits) can optionally select the boosting multiplying factor of the internal booster. according to the display status, power consumption can be reduced by changing the lcd drive duty and the lcd drive bias, and by controlling the boosting multiplying factor for the minimum requirements. for details, see the partial-display-on function section. due to the maximum boosting multiplying factor, the following external capacitor needs to be connected. for example, when the maximum boosting is quadrupled, the capacitors between c4+ and c4C for five- times boosting are not needed, so these pins must be open. table 18 vlout output status bt1 bt0 vlout output status 0 0 triple boosting output 0 1 quadruple boosting output 1 0 five-times boosting output 1 1 setting inhibited c1+ c1- vci + 1 f 0.47 f to 1 f vlout gnd + c2+ c2- + 0.47 f to 1 f vci c3+ c3- + 0.47 f to 1 f i) maximum five-times boosting ii) maximum quadruple boosting iii) maximum triple boosting c4+ c4- + 0.47 f to 1 f c1+ c1- vci + vlout gnd + c2+ c2- + vci c3+ c3- + c4+ c4- c1+ c1- vci + vlout gnd + c2+ c2- + vci c3+ c3- c4+ c4- 0.47 f to 1 f 0.47 f to 1 f 0.47 f to 1 f 0.47 f to 1 f 0.47 f to 1 f 1 f1 f figure 25 booster output multiplying factor switching
hd66740 51 example of power-supply voltage generator for more than five-times boosting output the hd66740 incorporates the booster for up to five-times boosting. however, the lcd drive voltage (vlcd) will not be e nough for five-times boosting from vcc when the power-supply voltage of vcc is low or when the lcd drive voltage is high for the high-contrast lcd display. in this case, the reference voltage (vci) for boosting can be set higher than the power-supply voltage of vcc. set the vci input voltage for the booster to 3.6 v or less within the range of vcc + 1.0 v. control the vci voltage so that the boosting output voltage (vlout) should be less than the absolute maximum ratings (17 v). + 1 f + + + 1 f 1 f 1 f seg1 to seg112 com1 to com80 c1+ c1- vci 1 f vlout gnd + c2+ c2- booster c3+ c3- c4+ c4- lcd driver regula -tor (2) regula -tor (1) vcc logic circuit 2.5 v 3.0 v vlcd gnd gnd gnd 3.0 x 5 = 15 v battery 3.6 v gnd (= 0 v) vcc (= 2.5 v) vcc (= 3 v) vlcd (= 15 v) hd66740 figure 26 usage example of booster at vci > vcc
hd66740 52 contrast adjuster software can adjust 64-step contrast for an lcd by varying the liquid-crystal drive voltage (potential difference between v lcd and v1) through the ct bits of the contrast adjustment register (electron volume function). the value of a variable resistor between v lcd and v1 (vr) can be precisely adjusted in a 0.05 x r unit within a range from 0.05 x r through 3.20 x r, where r is a reference resistance obtained by dividing the total resistance. the hd66740 incorporates a voltage-follower operational amplifier for each of v1 to v5 to reduce current flowing through the internal bleeder resistors, which generate different liquid-crystal drive voltages. thus, ct5-0 bits must be adjusted so that the potential differences between v lcd and v1 and between v5 and gnd are 0.4 v or higher when liquid-crystal drives, particularly when the vr is small. vr r r r0 r r gnd vlcd - + - + - + - + - + hd66740 ct v1 v2 v3 v4 v5 gnd figure 27 contrast adjuster
hd66740 53 table 19 contrast adjustment bits (ct) and variable resistor values 0 ct3 0 ct2 0 ct1 0 ct0 3.20 x r ct set value variable resistor value (vr) 0001 3.15 x r 0010 3.10 x r 0011 3.05 x r 0100 3.00 x r 0101 2.95 x r 0110 2.90 x r 0111 2.85 x r 0 ct4 0 0 0 0 0 0 0 100 1 2.75 x r 0 1010 2.70 x r 0 potential difference between v1 and gnd display color (small) (large) (light) (deep) 101 2.65 x r 0 1100 2.60 x r 0 1111 1.65 x r 1 0000 1.60 x r 0 0001 1.55 x r 0 0 010 1.50 x r 0 0 011 1.45 x r 0 0100 1.40 x r 0 0101 1.35 x r 0 0110 1.30 x r 0 0 111 1.25 x r 0 1 000 1.20 x r 0 100 1 1.15x r 1 1100 0.20 x r 1 1101 0.15 x r 1 1 110 0.10 x r 1 1 111 0.05 x r 1 100 0 2.80 x r 0 1 0 ct5 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
hd66740 54 table 20 contrast adjustment per bias drive voltage 9.5 x r + vr 9.5 x r x (v lcd - gnd) 0.748 x (v lcd -gnd) v dr 0.994 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] 9.5 x r + vr vr x (v lcd -gnd) 9.5 x r + vr r x (v lcd -gnd) 5 x r + vr 5 x r x (v lcd - gnd) 0.610 x (v lcd -gnd ) v dr 0.990 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] 5 x r + vr vr x (v lcd -gnd ) 5 x r + vr r x (v lcd -gnd ) 4 x r + vr 4 x r x (v lcd - gnd) 0.556 x (v lcd -gnd) v dr 0.988 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] 4 x r + vr vr x (v lcd -gnd) 4 x r + vr r x (v lcd -gnd) 9 x r + vr 9 x r x (v lcd - gnd) 0.737 x (v lcd -gnd) v dr 0.994 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] 9 x r + vr vr x (v lcd -gnd) 9 x r + vr r x (v lcd -gnd) 10 x r + vr 10 x r x (v lcd - gnd) 0.757 x (v lcd -gnd) v dr 0.995 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] vr x (v lcd -gnd) 10 x r + vr r x (v lcd -gnd) 10 x r + vr bias lcd drive voltage: v dr contrast adjustment range 1/10 bias drive 1/9.5 bias drive 1/9 bias drive 1/5 bias drive 1/4 bias drive - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : 8 x r + vr 8 x r x (v lcd - gnd) 0.714 x (v lcd -gnd) v dr 0.993 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] 8 x r + vr vr x (v lcd -gnd) 8 x r + vr r x (v lcd -gnd) 1/8 bias drive - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : 6 x r + vr 6 x r x (v lcd - gnd) 0.652 x (v lcd -gnd) v dr 0.992 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] vr x (v lcd -gnd) 6 x r + vr 6 x r + vr r x (v lcd -gnd) 7 x r + vr 7 x r x (v lcd - gnd) 0.686 x (v lcd -gnd) v dr 0.993 x (v lcd -gnd) 3 0.4 [v] 3 0.4 [v] vr x (v lcd -gnd) 7 x r + vr r x (v lcd -gnd) 7 x r + vr 1/7 bias drive 1/6 bias drive - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : : - lcd drive voltage adjustment range - limit of potential difference between v5 and gnd - limit if potential difference between vlcd and v1 : : :
hd66740 55 liquid crystal display drive bias selector an optimum liquid crystal display bias value can be selected using bs2-0 bits, according to the liquid crystal drive duty ratio setting (nl3-0 bits). liquid crystal display drive duty ratio and bias value can be displayed while switching software applications to match the lcd panel display status. the optimum bias value calculated using the following expression is an ideal value where the optimum contrast is obtained. driving by using a lower value than the optimum bias value provides lower contrast and lower liquid crystal display voltage (potential difference between v1 and gnd). when the liquid crystal display voltage is insufficient even if a five-times booster is used or output voltage is lowered because the battery life has been reached, the display can be made easier to see by lowering the liquid crystal bias. the liquid crystal display can be adjusted by using the contrast adjustment register (ct4-0 bits) and selecting the booster output level (bt1/0 bits). optimum bias value for 1/n duty ratio drive voltage = 1 n + 1 table 21 optimum drive bias values lcd drive duty ratio 1/80 1/72 1/64 1/56 1/48 1/40 1/32 1/24 1/16 1/8 (nl3-0 set value) 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 optimum drive bias value 1/10 1/9.5 1/9 1/8 1/8 1/7 1/6 1/6 1/5 1/4 (bs2-0 set value) 000 001 010 011 011 100 101 101 110 111
hd66740 56 vr v1 v2 v3 v4 v5 r r 6r r r v1 v2 v3,v4 v5 gnd r r r r i) 1/ 10 bias (bs2? = 000) vi) 1/ 4 bias (bs2? = 111) gnd vr vlcd vlcd note: r = reference resistor vr v1 v2 v3 v4 v5 r r 5.5r r r ii) 1/ 9.5 bias (bs2? = 001) vlcd vr v1 v2 v3 v4 v5 r r 5r r r iii) 1/ 9 bias (bs2? = 010) vlcd vr v1 v2 v3 v4 v5 r r 4r r r iv) 1/ 8 bias (bs2? = 011) vlcd vr gnd v1 v2 v3 v4 v5 r r 3r r r v) 1/7 bias (bs2? = 100) vlcd gndgndgndgndgnd gndgndgndgnd vr gnd v1 v2 v3 v4 v5 r r 2r r r v) 1/6 bias (bs2? = 101) vlcd gnd vr gnd v1 v2 v3 v4 v5 r r r r r v) 1/5 bias (bs2? = 110) vlcd gnd figure 28 liquid crystal display drive bias circuit
hd66740 57 lcd panel interface the hd66740 has a function for changing the common driver/segment driver output shift direction using the cms bit and sgs bit to meet the chip mounting positions of the hd66740. this is to fac ilitate the interface wiring to the lcd panel with cog or tcp installed. back of chip ?cms = 0 ?sgs = 0 seg112/1seg1/112 seg1/112 seg112/1 com9/72 seg1/112seg112/1 hitachi ltd. lcd controller/ driver:hd66740 >112 x 80 dots graphisc display >16 x 10 chracter display > >x4 booster >op-amp front of chip ?cms = 0 ?sgs = 1 com1/80 com72/9 seg112/1 seg1/112 com9/72 front of chip ?cms = 1 ?sgs = 0 back of chip ?cms = 1 ?sgs = 1 com41/40 com72/9 com80/1 com1/80 com8/73 com80/1 8 32 com9/72 com80/1 com1/80 com72/9 com41/40 com8/73 com73/8 com40/41 com72/9 com1/80 com8/72 com80/1 com73/8 com40/41 hitachi ltd. lcd controller/ driver:hd66740 >112 x 80 dots graphisc display >16 x 10 chracter display > >x4 booster >op-amp hitachi ltd. lcd controller/ driver:hd66740 >112 x 80 dots graphisc display >16 x 10 chracter display > >x4 booster >op-amp hitachi ltd. lcd controller/ driver:hd66740 >112 x 80 dots graphisc display >16 x 10 chracter display > >x4 booster >op-amp com73/8 com40/41 8 32 8 32 com41/40 com8/73 8 32 com73/8 com40/41 8 32 com41/40 com8/73 8 32 8 32 8 32 figure 29 1/80 duty drive pattern wiring
hd66740 58 lcd panel front of chip ?cms = 0 ?sgs = 1 com1/80 com72/9 seg112/1 seg1/112 com9/72 com41/40 com8/73 com80/1 com73/8 com40/41 figure 30 1-line display pattern wiring table 22 number of left and right extension lines of common driver drive duty ratio left edge of screen right edge of screen 1/48 16 (com1C8, 41C48) 32 (com9C40) 1/56 24 (com1C8, 41C56) 32 (com9C40) 1/64 32 (com1C8, 41C64) 32 (com9C40) 1/72 40 (com1C8, 41C72) 32 (com9C40) 1/80 40 (com1C8, 41C72) 40 (com9C40, 73C80)
hd66740 59 graphics display function in the graphics display mode, kanji characters, special symbols, and graphics icons can be displayed. up to 112 x 80-dot display is allowed using the cgram. thus, for a 12 x 13-dot kanji font, up to a 6-line x 9-character kanji display, and for a 14 x 15-dot kanji font, up to a 6-line x 8-character kanji display, and for a 16 x 16-dot kanji font, up to a 5-line x 6-character kanji display are allowed. i) 12 x 13-dot kanji display example (6-line x 9-character display) ii) 112 x 80-dot game display example figure 31 display example in graphics display mode vertical smooth scroll display the hd66740 can scroll character and graphics display vertically in units of raster-rows. this is achieved by writing display data into a one-line area that is not being used for display. in other words,
hd66740 60 one line can be used to achieve continuous smooth vertical scroll even in a 9-line or less display. here, after the 10th line is displayed, the first line is displayed again. when the 10th line is fully displayed, all one-line display data must be rewritten immediately after scrolling because there is no non-displayed area. additionally, when display areas of a graphics icon such as a pictogram or a menu bar are partially fixed-displayed, the remaining areas can be displayed. for details, see the partial smooth scroll display function section. specifically, this function is controlled by incrementing or decrementing the value in the display-start line bits (sl2 to sl0) and display-start raster-row bits (sn3 to sn0) by 1. for example, to smoothly scroll up, first set line bits sn3 to sn0 to 0000, and increment sl2 to sl0 by 1 from 000 to 111 to scroll seven raster-rows. then increment line bits sn3 to sn0 to 0001, and again increment sl2 to sl0 by 1 from 000 to 111. if the vertical double-height display is at the top of the line, scrolling is done by each two raster-row. when the response speed of the liquid crystal is low or when high-speed scro lling is needed, two- to four-raster-row scrolling is recommended.
hd66740 61 setting instructions (10-line display: nl3-0 = 1001) db7 db6db5 db4 db3 db2db1 db0r/w rs 0001 0 scroll up display set 96 x 80-dot initial display data to cgram cpu wait 00 10 0001 00 0 010 0001 00 0 010 0001 00 1 010 0001 0 0 1 10 0001 00 0 010 0001 00 0 010 0 0 update 1st-line (address 000 to 05fh) display data in cgram cpu wait cpu wait 0001 00 1 010 0001 0 10 10 0001 00 00 10 0001 00 0 0 0 cpu wait cpu wait 0001 00 1 010 0001 0 11 10 0001 00 0 010 0001 00 0 0 0 cpu wait 0001 00 1 010 sn3?n0 = 0000 sl2?l0 = 000 (1st raster-row of 1st line displayed at the top) scroll up 4 raster-rows (5th raster-row of 1st line displayed at the top) sn3?n0 = 0001 (1st raster-row of 2nd line displayed at the top) sl2?l0 = 000 update 1st-line (address 000 to 05fh) display data in cgram scroll up 12 raster-rows (5th raster-row of 2nd line displayed at the top) update 2nd-line (address 100 to 15fh) display data in cgram sn3?n0 = 0010 sl2?l0 = 000 (1st raster-row of 3rd line displayed at the top) update 2nd-line (address 100 to 15fh) display data in cgram scroll up 20 raster-rows (5th raster-row of 3rd line displayed at the top) update 3rd-line (address 200 to 25fh) display data in cgram sn3?n0 = 0011 sl2?l0 = 000 (1st raster-row of 4th line displayed at the top) update 3rd-line (address 200 to 25fh) display data in cgram scroll up 28 raster-rows (5th raster-row of 4th line displayed at the top) update 4th-line (address 300 to 35fh) display data in cgram cpu wait figure 32 setting instructions for vertical smooth scroll
hd66740 62 partial smooth scroll display function the hd66740 can partially fixed-display the areas of a graphics icon, such as a pictogram or a menu bar, and perform vertical smooth scrolling of the remaining bit-map areas. since the ps1 to ps0 bits do not perform smooth scrolling of the upper first to third display lines but does fixed-display, pictograms can be placed. when cn1 to cn0 bits are set to 10, the first line is displayed at the bottom edge of the lcd screen, and the menu bar can be fixed-displayed at the bottom. this function can largely control the bit-map rewrite frequencies and reduce software loads.
hd66740 63 table 23 bit setting and display lines 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line ps1? = 00 sn3? = 0000 sn3? = 0001 sn3? = 0010 com1 com80 ps1? = 01 com1 com80 ps1? = 10 com1 com80 ps1? = 11 com1 com80 sn3? = 0011 sn3? = 0011 sn3? = 0100 cn1? = 00 bit setting com position cn1? = 10 sn3? = 0000 sn3? = 0001 sn3? = 0010 sn3? = 0011 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 3rd line 4th line 2nd line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 3rd line 4th line 2nd line 6th line 7th line 8th line 9th line 10th line 1st line 2nd line 3rd line 4th line 5th line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 1st line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 1st line 1st line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 4th line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 1st line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 1st line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 1st line 1st line 5th line 6th line 7th line 8th line 9th line 10th line 2nd line 3rd line 4th line 1st line 2nd line 1st line 2nd line 1st line 2nd line 1st line 2nd line 1st line 2nd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 3rd line 5th line 6th line 7th line 8th line 9th line 3rd line 4th line 10th line 2nd line 2nd line 2nd line 2nd line 2nd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 1st line 1st line 1st line 1st line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 3rd line 5th line 6th line 7th line 8th line 9th line 3rd line 4th line 10th line 1st line 2nd line 3rd line 1st line 2nd line 3rd line 1st line 2nd line 3rd line 1st line 2nd line 3rd line 1st line 2nd line 3rd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 5th line 6th line 7th line 8th line 9th line 10th line 4th line 2nd line 3rd line 2nd line 3rd line 2nd line 3rd line 2nd line 3rd line 2nd line 3rd line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 1st line 1st line 1st line 1st line 1st line 2nd line 3rd line 4th line 5th line 6th line 7th line 8th line 3rd line 4th line 5th line 6th line 7th line 8th line 9th line 4th line 5th line 6th line 7th line 8th line 9th line 10th line 5th line 6th line 7th line 8th line 9th line 10th line 4th line notes: 1. the shadow lines above are fixed-displayed. they do not depend on the setting values of the sn3C0 or sl3C0 bits. 2. the sn3C0 and sl3C0 bits specify the next first scroll display line of the fixed-displayed lines. 3. when the drive duty ratio is nine lines (1/72 duty ratio) or less and cn1C0 is 10, the first line shifts to the last displayed line.
hd66740 64 partial smooth scroll display examples table 24 data setting to the cgram partial smooth scroll display examples cgram address cgram data "000" to "06f" "080" to "0ef" "100" to "16f" "180" to "1ef" "200" to "26f" "280" to "2ef" "300" to "36f" "380" to "3ef" "400" to "46f" "480" to "4ef" i) initial screen display - ps1-0 = "10" : fixed-displays the first and second lines - cn1-0 = "10" : moves the first line to the bottom edge - sn3-0 = "0010" : starts display from the third line - sl2-0 = "000" 2nd line (fixed display) scroll area 3rd line (display start position) 1st line (fixed display) figure 33 example of initial screen in the partial smooth scroll mode
hd66740 65 fixed display (2nd line) ii) four-dot partial scroll up - ps1-0 = "10" : fixed-displays the first and second lines - cn1-0 = "10" : moves the first line to the bottom edge - sn3-0 = "0010" : starts display from the third line - sl2-0 = "100" : shifts up by 4 dots display start setting position fixed display (1st line) figure 34 example of display screen in the partial smooth scroll mode (1) fixed display (2nd line) iii) 8-dot partial scroll up - ps1-0 = "10" : fixed-displays the first and second lines - cn1-0 = "10" : moves the first line to the bottom edge - sn3-0 = "001 1" : starts display from the fourth line - sl2-0 = "000" display start setting position fixed display (1st line) figure 35 example of display screen in the partial smooth scroll mode (2)
hd66740 66 double-height display the hd66740 can double the height of any desired line from the first to 10th lines. a line can be selected by the dl1 to dl10 bits as listed in table 25. all graphics display patterns stored in the cgram can be doubled in height, allowing easy recogn ition. note that there should be no space between the lines for double-height display (figure 36). in vertical smooth scrolling, when the display-start setting line is displaying at double height, scrolling can be done by each two-line (dot). table 25 double-height display specifications bit setting display position dl1 = 1 1st line: double-height dl2 = 1 2nd line: double-height dl3 = 1 3rd line: double-height dl4 = 1 4th line: double-height dl5 = 1 5th line: double-height dl6 = 1 6th line: double-height dl7 = 1 7th line: double-height dl8 = 1 8th line: double-height dl9 = 1 9th line: double-height dl10 = 1 10th line: double-height double height display (2nd line) double height display (8th line) - nl3-0 = "1001" (10-line display) - dl2 = 1 - dl8 = 1 figure 36 double-height display (2nd and 8th lines)
hd66740 67 reversed display function the hd66740 can display character/graphics display sections by black-and-white reversal. black- and-white reversal can be easily displayed when rev is set to 1. rev = 1 (reversed display) figure 37 reversed display
hd66740 68 partial-display-on function the hd66740 can program the liquid crystal display drive duty ratio se tting (nl3-0 bits), liquid crystal display drive bias value selection (bs2-0 bits), boost output level selection (bt1/0 bit) and contrast adjustment (ct5-0 bits). for example, in the 10-line display mode (1/80 duty ratio), the hd66740 can selectively drive only the center of the screen or only the top or bottom of the screen by combining these register functions and the centering display (cn1C0 bit) function. this is called partial-display-on. lowering the liquid crystal display drive duty ratio as required saves the liquid crystal display drive voltage, thus reducing internal current consumption. this is suitable for four-line display of a calendar or time, or the display of only graphics icons (pictograms) at the top or bottom of the screen, which needs to be continuous in the system standby state with minimal current consumption. here, the non- displayed lines are constantly driven by the unselected level voltage, thus turning off the lcd for the lines. in general, lowering the liquid crystal display drive duty ratio decreases the optimum liquid crystal display drive voltage and liquid crystal display drive bias value. this reduces output multiplying factors in the booster and greatly controls consumption current. table 26 partial-display-on function (10-line display) item normal 10-line display partial-on display (limited 4-line display) lcd screen 10th line displayed only four lines on the center of the screen (from the 3rd to 6th lines) only four lines at the top and bottom of the screen (from the 1st to 3rd and 10th lines) lcd drive position shift not necessary (cn1C0 = 00) necessary (cn1C0 = 01) necessary (cn1C0 = 01) lcd drive duty ratio 1/80 (nl3C0 = 1001) 1/32 (nl3C0 = 0011) 1/32 (nl3C0 = 0011) lcd drive bias value (optimum) 1/10 (bs2-0 = 000) 1/6 (bs2-0 = 101) 1/6 (bs2-0 = 101) lcd drive voltage* 12 v to 15 v (adjustable using ct5C0) 6 v to 8 v (adjustable using ct5C0) 6 v to 8 v (adjustable using ct5C0) boosting output multiplying factor five times (bt1C0 = 10) triple (bt1C0 = 00) triple (bt1C0 = 00) frame frequency (fosc = 90 khz) 70 hz 88 hz 88 hz note: the lcd drive voltage depends on the lcd materials which are actually used. since the lcd drive voltage is high when the lcd drive duty ratio is high, a low duty ratio is suitable for low-power consumption.
hd66740 69 - 1/32 duty drive at the top and bottom of the screen always applying non-selection level figure 38 partial-on display (date and time indicated) (1) - 1/32 duty drive at the center of the screen always applying selection level figure 39 partial-on display (date and time indicated) (2)
hd66740 70 sleep mode setting the sleep mode bit (slp) to 1 puts the hd66740 in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. specifically, lcd drive is completely halted. here, all the seg (seg1 to seg112) and com (com1 to com80) pins output the gnd level, resulting in no display. if the amp bit is set to 0 in the sleep mode, the lcd drive power supply can be turned off, reducing the total current consumption of the lcd module. table 27 comparison of sleep mode and standby mode function sleep mode (slp = 1) standby mode (stb = 1) lcd control turned off turned off r-c oscillation circuit operates normally halted
hd66740 71 standby mode setting the standby mode bit (stb) to 1 puts the hd66740 in the standby mode, where the device stops completely, halting all internal operations including the r-c oscillation circuit, thus further reducing current consumption compared to that in the sleep mode. specifically, character and segment displays, which are controlled by the multiplexing drive method, are completely halted. here, all the seg (seg1 to seg112) and com (com1 to com80) pins output the gnd level, resulting in no display. if the amp bit is set to 0 in the standby mode, the lcd drive power supply can be turned off. during the standby mode, no instructions can be accepted other than the start-oscillation. to cancel the standby mode, issue the start-oscillation instruction to stabilize r-c oscillation before setting the stb bit to 0. set standby mode: stb = 1 standby mode issue the start-oscillation instruction wait at least 10 ms cancel standby mode: stb = 0 turn on the lcd drive power supply: amp = 1 turn off the lcd power supply: amp = 0 figure 40 procedure for setting and canceling standby mode
hd66740 72 absolute maximum ratings item symbol unit value notes* power supply voltage (1) v cc v C0.3 to +4.6 1, 2 power supply voltage (2) v lcd C gnd v C0.3 to +16.0 1, 3 input voltage vt v C0.3 to v cc + 0.3 1 operating temperature topr c C40 to +85 1, 4 storage temperature tstg c C55 to +110 1, 5 notes: 1. if the lsi is used above these absolute maximum ratings, it may become permanently damaged. using the lsi within the following electrical characteristics limits is strongly recommended for normal operation. if these electrical characteristic conditions are also exceeded, the lsi will malfunction and cause poor reliability. 2. vcc > gnd must be maintained. 3. vlcd > gnd must be maintained. 4. for bare die and wafer products, specified up to 85?c. 5. this temperature specifications apply to the tcp package.
hd66740 73 dc characteristics (v cc = 1.8 to 3.6 v, ta = C40 to +85c* 1 ) item symbol min typ max unit test condition notes input high voltage v ih 0.7 v cc v cc v 2, 3 input low voltage v il C0.3 0.15 v cc vv cc = 1.8 to 2.7 v 2, 3 input low voltage v il C0.3 0.15 v cc vv cc = 2.7 to 3.6 v 2, 3 output high voltage (sda, db0-7 pins) v oh1 0.75 v cc vi oh = C0.1 ma 2, 4 output low voltage (sda, db0-7 pins) v ol1 0.2 v cc vv cc = 1.8 to 2.7 v, i ol = 0.1 ma 2 output low voltage (sda, db0-7 pins) v ol1 0.15 v cc vv cc = 2.7 to 3.6 v, i ol = 0.1 ma 2 driver on resistance (com pins) r com 3 20 k w id = 0.05 ma, v lcd = 10 v 5 driver on resistance (seg pins) r seg 3 30 k w id = 0.05 ma, v lcd = 10 v 5 i/o leakage current i li C1 1 a vin = 0 to v cc 6 pull-up mos current (db0-7, sda pins) -i p 1 1040av cc = 3 v, vin = 0 v 2 current consumption during normal operation (v cc Cgnd) i op 3 2 5 5 a r-c oscillation, v cc = 3 v, ta = 25 c, f osc = 86 khz (1/72 duty) 7, 8 current consumption during sleep mode (v cc Cgnd) i sl 1 1 a r-c oscillation, v cc = 3 v, ta = 25 c, f osc = 86 khz (1/72 duty) 7, 8 current consumption during standby mode (v cc Cgnd) i st 0.1 5 a v cc = 3 v, ta = 25c 7, 8 lcd drive power supply current (v lcd Cgnd) i lcd 2035av lcd = 12 v, ta = 25 c, f osc = 86 khz , 1/9 bias, vtest3=high 8 lcd drive voltage (v lcd C gnd) v lcd 4.5 15.0 v 9 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
hd66740 74 booster characteristics item symbol min typ max unit test condition notes triple-boost output voltage (vlout pin) v up3 8.5 8.9 9.0 v v cc = vci = 3.0 v, i o = 30 a, c = 1 f, f osc = 86 khz, ta = 25c 12 quadruple- boost output voltage (vlout pin) v up4 11.5 11.8 12.0 v v cc = vci = 3.0 v, i o = 30 a, c = 1 f, f osc = 86 khz, ta = 25c 12 five-times- boost output voltage (vlout pin) v up5 14.5 14.8 15.0 v v cc = vci = 3.0 v, i o = 30 a, c = 1 f, f osc = 86 khz, ta = 25c 12 use range of boost output voltage v up3 , v up4 , v up5 v cc 15.0 v for triple to five-times boost 12 note: for the numbered notes, refer to the electrical characteristics notes section following these tables.
hd66740 75 ac characteristics (v cc = 1.8 to 3.6 v, ta = C40 to +85c* 1 ) clock characteristics (v cc = 1.8 to 3.6 v) item symbol min typ max unit test condition notes external clock frequency fcp 50 75 100 khz 1 0 external clock duty ratio duty 45 50 55 % 1 0 external clock rise time trcp 0.2 s 10 external clock fall time tfcp 0.2 s 10 r-c oscillation clock f osc 69 86 103 khz rf = 270 k w , v cc = 3 v 11 note: for the numbered notes, refer to the electrical characteristics notes section following these tables. 68-system bus interface timing characteristics (vcc = 1.8 to 2.7 v) item symbol min typ max unit test condition enable cycle time write t cyce 600 ns figure 47 read t cyce 800 enable high-level pulse width write pw eh 120 ns figure 47 read pw eh 350 enable low-level pulse width write pw el 300 ns figure 47 read pw el 300 enable rise/fall time t er , t ef 25 ns figure 47 setup time (rs, r/w to e, cs*) t ase 50 ns figure 47 address hold time t ahe 20 ns figure 47 write data setup time t dswe 60 ns figure 47 write data hold time t he 20 ns figure 47 read data delay time t ddre 300 ns figure 47 read data hold time t dhre 5 n s figure 47
hd66740 76 (vcc = 2.7 to 3.6 v) item symbol min typ max unit test condition enable cycle time write t cyce 380 n s figure 47 read t cyce 500 enable high-level pulse width write pw eh 70 n s figure 47 read pw eh 250 enable low-level pulse width write pw el 150 n s figure 47 read pw el 150 enable rise/fall time t er , t ef 25 ns figure 47 setup time (rs, r/w to e, cs*) t ase 50 n s figure 47 address hold time t ahe 20 n s figure 47 write data setup time t dswe 60 n s figure 47 write data hold time t he 20 n s figure 47 read data delay time t ddre 200 ns figure 47 read data hold time t dhre 5 n s figure 47
hd66740 77 80-system bus interface timing characteristics (vcc = 1.8 to 2.7 v) item symbol min typ max unit test condition bus cycle time write t cycw 600 ns figure 48 read t cycr 800 ns figure 48 write low-level pulse width pw lw 120 ns figure 48 read low-level pulse width pw lr 350 ns figure 48 write high-level pulse width pw hw 300 ns figure 48 read high-level pulse width pw hr 300 ns figure 48 write/read rise/fall time t wrr , wrf 25 ns figure 48 setup time (rs to cs*, wr*, rd*) t as 50 ns figure 48 address hold time t ah 20 ns figure 48 write data setup time t dsw 60 ns figure 48 write data hold time t h 20 ns figure 48 read data delay time t ddr 300 ns figure 48 read data hold time t dhr 5 ns figure 48 (vcc = 2.7 to 3.6 v) item symbol min typ max unit test condition bus cycle time write t cycw 380 ns figure 48 read t cycr 500 ns figure 48 write low-level pulse width pw lw 70 ns figure 48 read low-level pulse width pw lr 250 ns figure 48 write high-level pulse width pw hw 150 ns figure 48 read high-level pulse width pw hr 150 ns figure 48 write/read rise/fall time t wrr, wrf 25 ns figure 48 setup time (rs to cs*, wr*, rd*) t as 50 ns figure 48 address hold time t ah 20 ns figure 48 write data setup time t dsw 60 ns figure 48 write data hold time t h 20 ns figure 48 read data delay time t ddr 200 ns figure 48 read data hold time t dhr 5 ns figure 48
hd66740 78 clock-synchronized serial interface timing characteristics (v cc = 1.8 to 3.6 v) (v cc = 1.8 to 2.55 v) item symbol min typ max unit test condition serial clock cycle time at write (receive) t scyc 0.5 2 0 s figure 49 at read (send) t scyc 1 20 s figure 49 serial clock high-level width at write (receive) t sch 230 ns figure 49 at read (send) t sch 480 ns figure 49 serial clock low-level width at write (receive) t scl 230 ns figure 49 at read (send) t scl 480 ns figure 49 serial clock rise/fall time t scf , t scr 2 0 n s figure 49 chip select setup time t csu 60 ns figure 49 chip select hold time t ch 200 ns figure 49 serial input data setup time t sisu 100 ns figure 49 serial input data hold time t sih 100 ns figure 49 serial output data delay time t sod 400 ns figure 49 serial output data hold time t soh 5 n s figure 49
hd66740 79 (v cc = 2.55 to 3.6 v) item symbol min typ max unit test condition serial clock cycle time at write (receive) t scyc 0.2 2 0 s figure 49 at read (send) t scyc 0.5 2 0 s figure 49 serial clock high-level width at write (receive) t sch 80 ns figure 49 at read (send) t sch 230 ns figure 49 serial clock low-level width at write (receive) t scl 80 ns figure 49 at read (send) t scl 230 ns figure 49 serial clock rise/fall time t scf , t scr 2 0 n s figure 49 chip select setup time t csu 60 ns figure 49 chip select hold time t ch 200 ns figure 49 serial input data setup time t sisu 40 ns figure 49 serial input data hold time t sih 40 ns figure 49 serial output data delay time t sod 200 ns figure 49 serial output data hold time t soh 5 n s figure 49 reset timing characteristics (v cc = 1.8 to 3.6 v) item symbol min typ max unit test condition reset low-level width t res 1 ms figure 50
hd66740 80 i2c bus interface timing characteristics (vcc = 1.8 to 3.6 v) item symbol min typ max unit test condition scl clock frequency f scl 0 1300 khz figure 51 scl clock high-level pulse width t sclh 120 ns figure 51 scl clock low-level pulse width t scll 240 ns figure 51 scl/sda rise time t sr 10 160 ns figure 51 scl/sda fall time t sf 10 7 0 n s figure 51 bus free time t buf 240 ns figure 51 start condition hold time t stah 320 ns figure 51 setup time for a repeated start condition t stas 320 ns figure 51 setup time for stop condition t stos 320 ns figure 51 sda data setup time t sdas 40 ns figure 51 sda data hold time t sdah 0 ns figure 51 scl/sda spike pulse width t sp 0 10 ns figure 51
hd66740 81 electrical characteristics notes 1. for bare die products, specified up to 85?c. 2. the following three circuits are i/o pin configurations (figure 41). pins: reset*, cs*, e/wr*/scl, rs, osc1, opoff, im2/1, im0/id, test pin: osc2 pmos nmos vcc gnd pin: rw/rd*/sda pmos nmos vcc gnd nmos pmos vcc (pull-up mos) vcc vcc pmos nmos (tri-state output circuit) gnd pmos (input circuit) pin: db7 to db0 nmos pmos vcc vcc pmos nmos (tri-state output circuit) output data output enable gnd im1 (input circuit) output data output enable im1 im2 figure 41 i/o pin configuration
hd66740 82 3. the test pin must be grounded and the im2/1, im0/id, and opoff pins must be grounded or connected to vcc. 4. corresponds to the high output for clock-synchronized serial interface. 5. applies to the resistor value (rcom) between power supply pins v1out, v2out, v5out, gnd and common signal pins, and resistor value (rseg) between power supply pins v1out, v3out, v4out, gnd and segment signal pins, when current id is flown through all driver output pins. 6. this excludes the current flowing through pull-up moss and output drive moss. 7. this excludes the current flowing through the input/output units. the input level must be fixed high or low because through current increases if the cmos input is left floating. 8. the following shows the relationship between the operation frequency (fosc) and current consumption (icc) (figure 42). 60 40 20 0 vcc = 3 v 0 display on (typ.) sleep (typ.) 30 20 10 0 vcc = 3 v, fosc = 86 khz 8.0 10.0 12.0 14.0 standby (typ.) 40 20 60 80 100 typ. iop ( a) ilcd ( a) r-c oscillation frequencies: fosc (khz) lcd drive voltage: vlcd (v) figure 42 relationship between the operation frequency and current consumption 9. each com and seg output voltage is within 0.15 v of the lcd voltage (vcc, v1, v2, v3, v4, v5) when there is no load. 10. applies to the external clock input (figure 43). oscillator osc1 open osc2 t rcp t fcp th tl 0.7vcc 0.5vcc 0.3vcc duty = th+tl th 100 1.5k to 2k figure 43 external clock supply
hd66740 83 11. applies to the internal oscillator operations using external oscillation resistor rf (figure 44 and table 28). osc1 osc2 rf since the oscillation frequency varies depending on the osc1 and osc2 pin capacitance, the wiring length to these pins should be minimized. figure 44 internal oscillation table 28 external resistance value and r-c oscillation frequency (referential data) external r-c oscillation frequency: fosc resistance (rf) vcc = 1.8 v vcc = 2.2 v vcc = 3.0 v vcc = 3.6 v 200 k w 89 khz 103khz 115 khz 121 khz 270 k w 70 khz 80 khz 88 khz 92 khz 300 k w 65 khz 73 khz 80 khz 83 khz 330 k w 60 khz 68 khz 74 khz 77 khz 360 k w 55 khz 62 khz 68 khz 71 khz 390 k w 52 khz 58 khz 64 khz 66 khz 430 k w 48 khz 53 khz 58 khz 60 khz 470 k w 44 khz 48 khz 52 khz 54 khz 12. booster characteristics test circuits are shown in figure 45. (five-times boosting) (quadruple boosting) gnd vcc 1 f vci c1+ c1- vlout + v lcd 1 f + gnd vcc vci c1+ c1- vlout + v lcd + 1 f c2+ c2- 1 f c3+ c3- c4+ c4- c2+ c2- c3+ c3- c4+ c4- ++ ++ + 1 f 1 f 1 f 1 f 1 f figure 45 booster
hd66740 84 4.03.02.01.0 4.0 8.0 12.0 16.0 vci (v) typ. 4.03.02.01.0 5.0 10.0 typ. vci (v) quadruple boosting 10060200-20-60 8.0 10.0 12.0 14.0 typ. 10060200-20-60 12.0 14.0 16.0 typ. 15.0 referential data vup4 = vlcd ?gnd; vup5 = vlcd ?gnd (i) relation between the obtained voltage and input voltage vup4 (v) vci = vcc, fosc = 86 khz, ta = 25 c dcc = 0 vup5 five-times boosting vci = vcc, fosc = 86 khz, ta = 25 c dcc = 0 (ii) relation between the obtained voltage and temperature quadruple boosting five-times boosting vup4 (v) vup5 vci = vcc = 3 v, fosc = 86 khz, io = 30 a dcc = 0 ta ( c) vci = vcc = 3 v, fosc = 86 khz, io = 30 a dcc = 0 ta ( c) 1.51.00.5 12.0 13.0 14.0 15.0 typ. 1.51.00.5 9.0 10.0 11.0 12.0 13.0 typ. 16.0 (iii) relation between the obtained voltage and capacity vup4 (v) vup5 (v) quadruple boosting five-times boosting c ( f) vci = vcc = 3.0 v, fosc = 86 khz, io = 30 a dcc = 0 c ( f) vci = vcc = 3.0 v, fosc = 86 khz, io = 30 a dcc = 0 figure 45 booster (cont)
hd66740 85 20015010050 0 9.5 10.0 11.5 12.0 12.5 typ. 20015010050 0 13.5 14.0 14.5 15.0 15.5 typ. quadruple boosting five-times boosting (iv) relation between the obtained voltage and current vup4 (v) vup5 (v) io ( a) vci = vcc = 3.0 v, fosc = 86 khz, ta = 25 c dcc = 0 io ( a) vci = vcc = 3.0 v, fosc = 86 khz, ta = 25 c dcc = 0 figure 45 booster (cont) load circuits ac characteristics test load circuits data bus: db7 to db0, sda test point 50 pf figure 46 load circuit
hd66740 86 timing characteristics 68-system bus operation rs r/w cs* e db0 to db7 db0 to db7 v ih v il t ase t ahe pw eh t ef t er t dswe t he write data t cyce t ddre t dhre v oh1 v ol1 v oh1 v ol1 read data v ih v il v il v il v ih v ih v il v ih v il v ih v il pw el v il v il *1 note 1: pw is specified in the overlapped period when cs* is low or e is high. eh figure 47 68-system bus timing
hd66740 87 80-system bus operation rs cs* wr* rd* db0 to db7 db0 to db7 v ih v il t as t ah pw lw, pw lr t wrf t wrr t dsw t hwr write data t cycw, t cycr t ddr t dhr v oh1 v ol1 v oh1 v ol1 read data v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih pw hw pw hr *1 note 1: pw and pw are specified in the overlapped period when cs* is low or wr* or rd* is low. lw lr figure 48 80-system bus timing
hd66740 88 clock-synchronized serial operation cs* scl sda t csu t sch v il t sisu tscr v ih v il v ih v il v ih v il t ch v ih v il v ih v il t cwl tscf t sih v il t scyc input data v ih start: s end: p input data sda t sod v oh1 v oh1 v oh1 v ol1 output data output data t soh v il figure 49 clock-synchronized serial interface timing reset operation reset* v il v il t res figure 50 reset timing
hd66740 89 i2c bus operation scl t bu f vil2 vil2 vih start : s vih vih sd a t s dah vih t sf vil2 vih vih t scl l t sc lh t scl t stah t sr vil2 vih t stas t sdas t stos stop : p re peat ed start : sr vil2 t sp vih s top : p figure 51 i2c bus interface timing
hd66740 90 power-on/off sequence to prevent pulse lighting of lcd screens at power-on/off, the power-on/off sequence is activated as shown below. however, since the sequence depends on lcd materials to be used, confirm the conditions by using your own system. power-on sequence turn on power voltages vcc and vci, reset = "low" wait for 1 ms or longer (power-on time) wait for 10 ms or longer (oscillation stabilization time) issue use-state instruction turned on display: d = 1 wait for 10-150 ms or longer (op-amplifier output stabilization time) issue lcd power instruction note: depends on the external capacitance of v1out to v5out. figure 52 power-on sequence
hd66740 91 signal-input instruction issued power voltage: vcc vcc gnd reset oscillation state vcc gnd vcc gnd power-on reset time: 1 ms oscillation stabilization time: 10 ms note: cr oscillation starts by power-on and input reset. the standby mode is cleared by input reset. figure 53 power-on timing
hd66740 92 power-off sequence issue lcd power instruction turn off display: d = 0 turn off power voltages vcc and vci to the power-on sequence figure 54 power-off sequence power voltage: vcc vcc gnd reset vcc gnd v1out gnd power is turned off. reset is input as soon as possible. driver seg/ com output note: when hardware reset is input during the power-off period, the d bit is cleared to 0 and seg/com output is forcibly lowered to the gnd level. figure 55 power-off timing
hd66740 modification history revision 0.1 (feb. 15. 2000) - first release revision 0.2 (5. may. 2000) - change pad pitch from 60um to 50um. - added lcd-driving-pattern control instruction revision 0.3 (1. july. 2000) - added pad arrangement figure and coordinate table - change figure 41 (remove pull-up mos from db7 to db0) revision 0.4 (september. 2000) - added rs pin explanation when serial interface mode is used. - added standard tcp (tb0) drawing. revision 0.5 (november. 2000) - remove cursor display related explanations. - remove character and super-imposed display related explanations. revision 0.6 (january. 2001) - support 1.8v low voltage operation. - corrected corner pad number (p6). - added vtest usage (p48) and operational amplifier usage (p49). - changed r-c oscillation frequency of table 28 (p83). - added i2c interface (HCD66740wbp, hd66740wtb0). revision 0.7 (january. 2001) - added power on/off sequence.
hd66740 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all right reserved: no one is permitted to reproduce or duplicated, in any form, the whole or part of this document without hitachi's permission. 3. hitachi will not be held res ponsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi's semiconductor products. hitachi assumes no responsib ility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party of hitachi, ltd. 6. medical applications: hitachi's products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi's sales company. such use includes, but is not limited to use in life support systems. buyers of hitachi's products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications.

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